| Message ID | 1389007857-14649-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 6 January 2014 11:30, Peter Maydell <peter.maydell@linaro.org> wrote:
> First target-arm pull request of the year; please pull.
...and first brown-paper-bag bug of the year: this
breaks booting of Linux when emulating ARMv7 32 bit
CPUs.
Please ignore this pull request. I'll fix things up
and resubmit. (I'm also planning to add some more
patches which made it through review yesterday,
since they include softfloat fixes which are also
required for PPC, and I agreed with Alex that we'd
run those through my tree and let the PPC patchset
hold briefly until they got committed.)
Apologies for this error.
thanks
-- PMM
First target-arm pull request of the year; please pull. (Incidentally I like the way these pull requests have a broad distribution of patch authors. The last 62-patch monster had 9 different authors, this one has 10, and the one from earlier in December had 9...) thanks -- PMM The following changes since commit f976b09ea249cccc3fd41c98aaf6512908db0bae: PPC: Fix compilation with TCG debug (2013-12-22 19:15:55 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140106 for you to fetch changes up to 449d14c182dd5d2d8d06bc1c36074533309274b6: hw: arm_gic: Introduce gic_set_priority function (2014-01-06 11:16:48 +0000) ---------------------------------------------------------------- target-arm queue: * further A64 decoder patches, including enabling the aarch64-linux-user target, since we can now run at least some programs (FP and Neon instruction support is not yet complete) * cadence UART model fixes * some minor bug fixes and cleanups ---------------------------------------------------------------- Alex Bennée (6): target-arm: A64: add support for ld/st unsigned imm target-arm: A64: add support for ld/st with reg offset target-arm: A64: add support for ld/st with index target-arm: A64: add support for add, addi, sub, subi target-arm: A64: add support for move wide instructions .travis.yml: Add aarch64-* targets Alexander Graf (8): target-arm: A64: add support for 3 src data proc insns target-arm: A64: implement SVC, BRK target-arm: aarch64: add support for ld lit target-arm: A64: Add support for dumping AArch64 VFP register state target-arm: A64: Add "Floating-point data-processing (2 source)" insns target-arm: A64: Add "Floating-point data-processing (3 source)" insns target-arm: A64: Add fmov (scalar, immediate) instruction target-arm: Give the FPSCR rounding modes names Christoffer Dall (2): arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER hw: arm_gic: Introduce gic_set_priority function Claudio Fontana (6): target-arm: A64: add support for add/sub with carry target-arm: A64: add support for conditional compare insns linux-user: AArch64: define TARGET_CLONE_BACKWARDS target-arm: A64: Add support for floating point compare target-arm: A64: Add support for floating point conditional compare target-arm: A64: Add support for floating point cond select Michael Matz (1): target-arm: A64: support for ld/st/cl exclusive Michael S. Tsirkin (1): target-arm: fix build with gcc 4.8.2 Peter Crosthwaite (13): char/cadence_uart: Mark struct fields as public/private char/cadence_uart: Add missing uart_update_state char/cadence_uart: Fix reset. char/cadence_uart: s/r_fifo/rx_fifo char/cadence_uart: Simplify status generation char/cadence_uart: Define Missing SR/ISR fields char/cadence_uart: Remove TX timer & add TX FIFO state char/cadence_uart: Fix can_receive logic char/cadence_uart: Use the TX fifo for transmission char/cadence_uart: Delete redundant rx rst logic char/cadence_uart: Implement Tx flow control target-arm: remove raw_read|write duplication arm/xilinx_zynq: Always instantiate the GEMs Peter Maydell (13): target-arm: A64: add support for ld/st pair target-arm: A64: Add decoder skeleton for FP instructions target-arm: A64: implement FMOV target-arm: Pull "add one cpreg to hashtable" into its own function target-arm: Update generic cpreg code for AArch64 target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder target-arm: A64: Implement MRS/MSR/SYS/SYSL target-arm: A64: Implement minimal set of EL0-visible sysregs target-arm: Widen thread-local register state fields to 64 bits target-arm: Widen exclusive-access support struct fields to 64 bits default-configs: Add config for aarch64-linux-user target-arm: A64: Fix vector register access on bigendian hosts target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum Sergey Fedorov (1): target-arm: use c13_context field for CONTEXTIDR Will Newton (1): linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext .travis.yml | 1 + default-configs/aarch64-linux-user.mak | 3 + hw/arm/xilinx_zynq.c | 17 +- hw/char/cadence_uart.c | 153 +- hw/intc/arm_gic.c | 27 +- hw/intc/arm_gic_common.c | 4 +- hw/intc/gic_internal.h | 7 +- include/hw/intc/arm_gic_common.h | 2 +- linux-user/aarch64/syscall.h | 1 + linux-user/aarch64/target_cpu.h | 5 +- linux-user/arm/target_cpu.h | 2 +- linux-user/main.c | 154 +- linux-user/signal.c | 10 +- target-arm/cpu.h | 122 +- target-arm/cpu64.c | 6 + target-arm/helper-a64.c | 45 + target-arm/helper-a64.h | 4 + target-arm/helper.c | 335 +++-- target-arm/helper.h | 15 +- target-arm/kvm-consts.h | 37 + target-arm/machine.c | 12 +- target-arm/neon_helper.c | 12 - target-arm/translate-a64.c | 2494 ++++++++++++++++++++++++++++++-- target-arm/translate.c | 88 +- target-arm/translate.h | 2 + 25 files changed, 3152 insertions(+), 406 deletions(-) create mode 100644 default-configs/aarch64-linux-user.mak