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[129.42.161.36]) by mx.google.com with ESMTPSA id f5sm22839079qas.11.2014.01.03.10.22.45 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 03 Jan 2014 10:22:47 -0800 (PST) From: Tom Musta To: qemu-devel@nongnu.org Date: Fri, 3 Jan 2014 12:22:04 -0600 Message-Id: <1388773331-787-8-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1388773331-787-1-git-send-email-tommusta@gmail.com> References: <1388773331-787-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22c Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V5 PATCH 07/14] target-ppc: VSX Stage 4: Add xsmulsp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp) instruction. The existing VSX_MUL macro is modified to support rounding of the intermediate result to single precision. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- V2: Updated conversion to single precision. target-ppc/fpu_helper.c | 13 +++++++++---- target-ppc/helper.h | 1 + target-ppc/translate.c | 2 ++ 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index f047640..dc9849f 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1822,7 +1822,7 @@ VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_MUL(op, nels, tp, fld, sfprf) \ +#define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xa, xb; \ @@ -1849,6 +1849,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ \ + if (r2sp) { \ + xt.fld[i] = helper_frsp(env, xt.fld[i]); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[i], sfprf); \ } \ @@ -1858,9 +1862,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_MUL(xsmuldp, 1, float64, f64, 1) -VSX_MUL(xvmuldp, 2, float64, f64, 0) -VSX_MUL(xvmulsp, 4, float32, f32, 0) +VSX_MUL(xsmuldp, 1, float64, f64, 1, 0) +VSX_MUL(xsmulsp, 1, float64, f64, 1, 1) +VSX_MUL(xvmuldp, 2, float64, f64, 0, 0) +VSX_MUL(xvmulsp, 4, float32, f32, 0, 0) /* VSX_DIV - VSX floating point divide * op - instruction mnemonic diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 696b9d3..0ccdc96 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -288,6 +288,7 @@ DEF_HELPER_2(xsrdpiz, void, env, i32) DEF_HELPER_2(xsaddsp, void, env, i32) DEF_HELPER_2(xssubsp, void, env, i32) +DEF_HELPER_2(xsmulsp, void, env, i32) DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c50d800..3a6a94b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7360,6 +7360,7 @@ GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) @@ -10169,6 +10170,7 @@ GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), +GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),