| Message ID | 1388771759-27052-1-git-send-email-festevam@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | Stefano Babic |
| Headers | show |
Hi Stefano, On Fri, Jan 3, 2014 at 3:55 PM, Fabio Estevam <festevam@gmail.com> wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > Provide an argument to enable_fec_anatop_clock() to specify the clock frequency > that will be generated. > > No changes are made to mx6slevk, which uses the default 50MHz fec clock. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > Stefano, > > I don't have access to a mx6slevk board at the moment, but will test it on > Monday. Wanted to submit it so that people could provide some feedback on the > series. > > mx6slevk is using the default clock of 50MHz, so I kept it unchanged. Just tested on a mx6slevk and confirmed that FEC is functional after this patch. Regards, Fabio Estevam
Hi Fabio, On 06/01/2014 14:12, Fabio Estevam wrote: > Hi Stefano, > > On Fri, Jan 3, 2014 at 3:55 PM, Fabio Estevam <festevam@gmail.com> wrote: >> From: Fabio Estevam <fabio.estevam@freescale.com> >> >> Provide an argument to enable_fec_anatop_clock() to specify the clock frequency >> that will be generated. >> >> No changes are made to mx6slevk, which uses the default 50MHz fec clock. >> >> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> >> --- >> Stefano, >> >> I don't have access to a mx6slevk board at the moment, but will test it on >> Monday. Wanted to submit it so that people could provide some feedback on the >> series. >> >> mx6slevk is using the default clock of 50MHz, so I kept it unchanged. > > Just tested on a mx6slevk and confirmed that FEC is functional after this patch. > Thanks for testing - patch is ok for me. Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic
On 03/01/2014 18:55, Fabio Estevam wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > Provide an argument to enable_fec_anatop_clock() to specify the clock frequency > that will be generated. > > No changes are made to mx6slevk, which uses the default 50MHz fec clock. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fcc4f35..c0805b3 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -322,7 +322,7 @@ static u32 get_mmdc_ch0_clk(void) #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(void) +int enable_fec_anatop_clock(enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -330,7 +330,13 @@ int enable_fec_anatop_clock(void) struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + if (freq < ENET_25MHz || freq > ENET_125MHz) + return -EINVAL; + reg = readl(&anatop->pll_enet); + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= freq; + if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 93f29a7..e31ba0a 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -42,6 +42,13 @@ enum mxc_clock { MXC_I2C_CLK, }; +enum enet_freq { + ENET_25MHz, + ENET_50MHz, + ENET_100MHz, + ENET_125MHz, +}; + u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); @@ -50,5 +57,5 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); -int enable_fec_anatop_clock(void); +int enable_fec_anatop_clock(enum enet_freq freq); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 643fdac..47c04ce 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -128,7 +128,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(); + ret = enable_fec_anatop_clock(ENET_50MHz); if (ret) return ret;