Patchwork [7/7] clk: tegra: use max divider if divider overflows

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Submitter Andrew Bresticker
Date Dec. 27, 2013, 12:44 a.m.
Message ID <1388105067-24438-8-git-send-email-abrestic@chromium.org>
Download mbox | patch
Permalink /patch/305326/
State Not Applicable, archived
Headers show

Comments

Andrew Bresticker - Dec. 27, 2013, 12:44 a.m.
When requesting a rate less than the minimum clock rate for a divider,
use the maximum divider value instead of bailing out with an error.
This matches the behavior of the generic clock divider.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
 drivers/clk/tegra/clk-divider.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 4d75b1f..290f9c1 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -59,7 +59,7 @@  static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
 		return 0;
 
 	if (divider_ux1 > get_max_div(divider))
-		return -EINVAL;
+		return get_max_div(divider);
 
 	return divider_ux1;
 }