From patchwork Fri Dec 27 00:44:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 305325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C2DDD2C0095 for ; Fri, 27 Dec 2013 11:51:46 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753997Ab3L0Avp (ORCPT ); Thu, 26 Dec 2013 19:51:45 -0500 Received: from mail-qc0-f202.google.com ([209.85.216.202]:62107 "EHLO mail-qc0-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753995Ab3L0Avo (ORCPT ); Thu, 26 Dec 2013 19:51:44 -0500 Received: by mail-qc0-f202.google.com with SMTP id i17so558871qcy.5 for ; Thu, 26 Dec 2013 16:51:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dNmSrIq2muW2ro5aZfMgULOmMrYHqcwn71RccB7JeSY=; b=UKmOwTu+vPp8Zb8ywdTnPS6SwAC5TdmaO4cBPSjLVd/m0GqDCYYDfcjEeBh7aVs/Gg FgLTuXM784Am88aQ7D7uYMJkqxcGWXPcMhc1gVQJrNF80JHv5CbfHFd1Sr/5s3v8Hba7 WD4kD1Mo3y3qDJSt+IAv2N1gKmD1PyEduzfQSQr//XO0bLndvw42cMjDusXih7EVFnHf BlfBK/iOW0GQv7KeiwnZqRI8M9j04yeZ1uT5O5V76Ld6lhVn0KZs+/HsEu5PdX+vmykm 8dBUl2Xgz4UcgB82OAhugUeZHMVt9/qPZsBxbwNRSTttdSjElOatNYpIIgN2Yq927Rsy X4yQ== X-Gm-Message-State: ALoCoQlHg4FrWfWjYjPQHJab6QHIWvU96rwtysQ5oNYhLWl5w3cfgs4Bv2jKqOHefol1bD9hJ1ZlA53cbBDgHWGo15UHjm/2m8t9AoEitj3S2ex1Aebc66rmlr3fq3LulJiVcueqdUMFag1dswuRkmayOwfhAOt2KCQZK2uxZPvnCL0tgGWpUD8FZEg8wVl0VY9g9uAwy9Orc1nYFpgy9dapsrMJn0fFCQ== X-Received: by 10.58.249.180 with SMTP id yv20mr16543618vec.11.1388105088308; Thu, 26 Dec 2013 16:44:48 -0800 (PST) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id l41si10141077yhi.5.2013.12.26.16.44.48 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Dec 2013 16:44:48 -0800 (PST) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 27D6131C107; Thu, 26 Dec 2013 16:44:48 -0800 (PST) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id DD3B4220798; Thu, 26 Dec 2013 16:44:47 -0800 (PST) From: Andrew Bresticker To: Mike Turquette , Stephen Warren Cc: Thierry Reding , Peter De Schrijver , Prashant Gaikwad , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rhyland Klein , Andrew Bresticker Subject: [PATCH 2/7] clk: tegra: Fix PLLD mnp table Date: Thu, 26 Dec 2013 16:44:22 -0800 Message-Id: <1388105067-24438-3-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1388105067-24438-1-git-send-email-abrestic@chromium.org> References: <1388105067-24438-1-git-send-email-abrestic@chromium.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Rhyland Klein PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein Signed-off-by: Andrew Bresticker --- drivers/clk/tegra/clk-tegra124.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 28bb238..14c3f2f 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -570,6 +570,15 @@ static struct tegra_clk_pll_params pll_a_params = { .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, }; +static struct div_nmp plld_nmp = { + .divm_shift = 0, + .divm_width = 5, + .divn_shift = 8, + .divn_width = 11, + .divp_shift = 20, + .divp_width = 3, +}; + static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { {12000000, 216000000, 864, 12, 4, 12}, {13000000, 216000000, 864, 13, 4, 12}, @@ -603,7 +612,7 @@ static struct tegra_clk_pll_params pll_d_params = { .lock_mask = PLL_BASE_LOCK, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_delay = 1000, - .div_nmp = &pllp_nmp, + .div_nmp = &plld_nmp, .freq_table = pll_d_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,