From patchwork Fri Dec 27 00:44:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 305322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 17B7B2C0095 for ; Fri, 27 Dec 2013 11:46:15 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754039Ab3L0ApG (ORCPT ); Thu, 26 Dec 2013 19:45:06 -0500 Received: from mail-oa0-f73.google.com ([209.85.219.73]:43863 "EHLO mail-oa0-f73.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753996Ab3L0Aow (ORCPT ); Thu, 26 Dec 2013 19:44:52 -0500 Received: by mail-oa0-f73.google.com with SMTP id i4so1932994oah.4 for ; Thu, 26 Dec 2013 16:44:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FpEojSu+HSG8OlIap6ZeEYxutLcb/+e9gdlnDqbqak0=; b=VTn99B8ku8mGtsgnKt4kUZugHIfe3odWW7YGFOdZq506vzDGXVFDsStEMj/r+Rv2sl aHaFDYuvJ/YJ3CNSemVKNwqhGLeotfwKLQoqcHmIz9eaSho+z4UeodxDRVduet3FBFhs i6iK6BsrW/+9uqjCIONSEgwuroTj54lTVq2Z+lmW+f9sLhQyihUN8B4fFIEfYUkBP5kR p7h7Fhfi6OGF4aEHkpgNg50YJLtyUJwQfK3KUj+oAXzuT5L7I6PdzLIFO+SRDDyVHy7r weYYqPKCYOY3Dl/qH27lcfiWK6Y38fKQ4M0uZnRwGHFQWuhc17os324B6v9vVGbUzBFl 61zw== X-Gm-Message-State: ALoCoQl8Ib38vTjU5jui+4YMROG4Dty3ckJXqaX7zNgT28HavCejHpR/GdDY0ZLRZtL5+2Hy46MYoP2xeuPnZkDwNIMyoEHczueSH73c+vDr71cjJfVpi2W4ap8TEdRDK8/gJuvPOiUo8ZAlEt7TJrgrqdjUbQ/pxIA/rQ5j7Bna9QVu55emvGrl5HaUceOklJTiNWYWRg96jfnHVopjGNTVvvBg0gvlDg== X-Received: by 10.43.44.136 with SMTP id ug8mr17035589icb.17.1388105089306; Thu, 26 Dec 2013 16:44:49 -0800 (PST) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id d9si10143061yhl.2.2013.12.26.16.44.49 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Dec 2013 16:44:49 -0800 (PST) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id 214F55A41B6; Thu, 26 Dec 2013 16:44:49 -0800 (PST) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id D7410220798; Thu, 26 Dec 2013 16:44:48 -0800 (PST) From: Andrew Bresticker To: Mike Turquette , Stephen Warren Cc: Thierry Reding , Peter De Schrijver , Prashant Gaikwad , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, David Ung , Andrew Bresticker Subject: [PATCH 3/7] clk: tegra: PLLD2 fixes for hdmi Date: Thu, 26 Dec 2013 16:44:23 -0800 Message-Id: <1388105067-24438-4-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1388105067-24438-1-git-send-email-abrestic@chromium.org> References: <1388105067-24438-1-git-send-email-abrestic@chromium.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: David Ung Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung Signed-off-by: Andrew Bresticker --- drivers/clk/tegra/clk-tegra124.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 14c3f2f..0fc9126 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -619,12 +619,11 @@ static struct tegra_clk_pll_params pll_d_params = { }; static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { - { 12000000, 148500000, 99, 1, 8}, - { 12000000, 594000000, 99, 1, 1}, - { 13000000, 594000000, 91, 1, 1}, /* actual: 591.5 MHz */ - { 16800000, 594000000, 71, 1, 1}, /* actual: 596.4 MHz */ - { 19200000, 594000000, 62, 1, 1}, /* actual: 595.2 MHz */ - { 26000000, 594000000, 91, 2, 1}, /* actual: 591.5 MHz */ + { 12000000, 594000000, 99, 1, 2}, + { 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */ + { 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */ + { 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */ + { 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -1295,9 +1294,9 @@ static void __init tegra124_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_d2", NULL); clks[TEGRA124_CLK_PLL_D2] = clk; - /* PLLD2_OUT0 ?? */ + /* PLLD2_OUT0 */ clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", - CLK_SET_RATE_PARENT, 1, 2); + CLK_SET_RATE_PARENT, 1, 1); clk_register_clkdev(clk, "pll_d2_out0", NULL); clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;