diff mbox

[U-Boot,v2,5/6] mx6: soc: Add the required LDO ramp up delay

Message ID 1388076695-28174-5-git-send-email-festevam@gmail.com
State Accepted
Delegated to: Stefano Babic
Headers show

Commit Message

Fabio Estevam Dec. 26, 2013, 4:51 p.m. UTC 
From: Fabio Estevam <fabio.estevam@freescale.com>

When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None

 arch/arm/cpu/armv7/mx6/soc.c | 22 +++++++++++++++++++---
 include/configs/mx6_common.h |  1 +
 2 files changed, 20 insertions(+), 3 deletions(-)

Comments

Stefano Babic Jan. 2, 2014, 4:20 p.m. UTC | #1 
On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> When changing LDO voltages we need to wait for the required amount of time
> for the voltage to settle.
> 
> Also, as the timer is still not available when arch_cpu_init() is called, we
> need to call it later at board_postclk_init() phase.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ee888ce..3aa3bb0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -124,7 +124,7 @@  static void clear_ldo_ramp(void)
 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 val, reg = readl(&anatop->reg_core);
+	u32 val, step, old, reg = readl(&anatop->reg_core);
 	u8 shift;
 
 	if (mv < 725)
@@ -150,9 +150,20 @@  static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 		return -EINVAL;
 	}
 
+	old = (reg & (0x1F << shift)) >> shift;
+	step = abs(val - old);
+	if (step == 0)
+		return 0;
+
 	reg = (reg & ~(0x1F << shift)) | (val << shift);
 	writel(reg, &anatop->reg_core);
 
+	/*
+	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+	 * step
+	 */
+	udelay(3 * step);
+
 	return 0;
 }
 
@@ -170,8 +181,6 @@  int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
-
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
 #ifdef CONFIG_APBH_DMA
@@ -182,6 +191,13 @@  int arch_cpu_init(void)
 	return 0;
 }
 
+int board_postclk_init(void)
+{
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
+	return 0;
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 674bcd3..514d634 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -20,5 +20,6 @@ 
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
+#define CONFIG_BOARD_POSTCLK_INIT
 
 #endif