diff mbox

[U-Boot,6/6] mx6: soc: Disable VDDPU regulator

Message ID c901e51007e54684b7734d4b93a9e5d0@BY2PR03MB379.namprd03.prod.outlook.com
State Not Applicable
Delegated to: Stefano Babic
Headers show

Commit Message

Ranjani.Vaidyanathan@freescale.com Dec. 24, 2013, 3:30 p.m. UTC 
Hi Fabio,

The PU power-up/power-down sequence has specific steps, includes some clock management. Please refer to the kernel code for the sequence.

Thanks,
Ranjani

-----Original Message-----
From: Fabio Estevam [mailto:festevam@gmail.com] 
Sent: Wednesday, December 18, 2013 9:16 PM
To: sbabic@denx.de
Cc: Huang Yongcai-B20788; Liu Hui-R64343; Vaidyanathan Ranjani-RA5478; eric.nelson@boundarydevices.com; troy.kisky@boundarydevices.com; u-boot@lists.denx.de; Estevam Fabio-R49496
Subject: [PATCH 6/6] mx6: soc: Disable VDDPU regulator

From: Fabio Estevam <fabio.estevam@freescale.com>

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c             | 23 +++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h | 23 +++++++++++++++++++++++
 2 files changed, 46 insertions(+)

--
1.8.1.2

Comments

Fabio Estevam Dec. 26, 2013, 5 p.m. UTC | #1 
On Tue, Dec 24, 2013 at 1:30 PM, Ranjani.Vaidyanathan@freescale.com
<Ranjani.Vaidyanathan@freescale.com> wrote:
> Hi Fabio,
>
> The PU power-up/power-down sequence has specific steps, includes some clock management. Please refer to the kernel code for the sequence.

Thanks for the review, Ranjani.

Just sent v2 that disables vddpu in the same way as in kernel.

Regards,

Fabio Estevam
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 9dc30ba..243226e 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -19,6 +19,8 @@ 
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+#define VDDPU_MASK	(0x1f << 9)
+
 enum ldo_reg {
 	LDO_ARM,
 	LDO_SOC,
@@ -177,11 +179,32 @@  static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
+static void imx_set_vddpu_power_down(void) {
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
+
+	u32 val;
+
+	/* need to power down xPU in GPC before turning off PU LDO */
+	val = readl(&gpc->gpu_ctrl);
+	writel(val | 0x1, &gpc->gpu_ctrl);
+
+	val = readl(&gpc->ctrl);
+	writel(val | 0x1, &gpc->ctrl);
+	while (readl(&gpc->ctrl) & 0x1)
+		;
+
+	/* disable VDDPU */
+	writel(VDDPU_MASK, &anatop->reg_core_clr); }
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+	imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7ef7152..fb0c4c7 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -659,5 +659,28 @@  struct wdog_regs {
 	u16	wmcr;	/* Miscellaneous Control */
 };
 
+struct gpc_regs {
+	u32	ctrl;		/* 0x000 */
+	u32	pgr;		/* 0x004 */
+	u32	imr1;		/* 0x008 */
+	u32	imr2;		/* 0x00c */
+	u32	imr3;		/* 0x010 */
+	u32	imr4;		/* 0x014 */
+	u32	isr1;		/* 0x018 */
+	u32	isr2;		/* 0x01c */
+	u32	isr3;		/* 0x020 */
+	u32	isr4;		/* 0x024 */
+	u32	reserved1[0x86];
+	u32	gpu_ctrl;	/* 0x260 */
+	u32	gpu_pupscr;	/* 0x264 */
+	u32	gpu_pdnscr;	/* 0x268 */
+	u32	gpu_sr;		/* 0x26c */
+	u32	reserved2[0xc];
+	u32	cpu_ctrl;	/* 0x2a0 */
+	u32	cpu_pupscr;	/* 0x2a4 */
+	u32	cpu_pdnscr;	/* 0x2a8 */
+	u32	cpu_sr;		/* 0x2ac */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */