@@ -86,9 +86,10 @@ struct eeh_pe {
*/
#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
-#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
-#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
-#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
+#define EEH_DEV_US_PORT (1 << 2) /* Upstream port */
+#define EEH_DEV_DS_PORT (1 << 3) /* Downstream port */
+#define EEH_DEV_IRQ_DISABLED (1 << 4) /* Interrupt disabled */
+#define EEH_DEV_DISCONNECTED (1 << 5) /* Removing from PE */
#define EEH_DEV_SYSFS (1 << 8) /* Sysfs created */
@@ -99,6 +100,7 @@ struct eeh_dev {
int pe_config_addr; /* PE config address */
u32 config_space[16]; /* Saved PCI config space */
u8 pcie_cap; /* Saved PCIe capability */
+ int aer_cap; /* Saved AER capability */
struct eeh_pe *pe; /* Associated PE */
struct list_head list; /* Form link list in the PE */
struct pci_controller *phb; /* Associated PHB */
@@ -128,9 +128,12 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
edev->mode |= EEH_DEV_BRIDGE;
if (pci_is_pcie(dev)) {
edev->pcie_cap = pci_pcie_cap(dev);
-
+ edev->aer_cap = pci_find_ext_capability(dev,
+ PCI_EXT_CAP_ID_ERR);
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
edev->mode |= EEH_DEV_ROOT_PORT;
+ else if (pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)
+ edev->mode |= EEH_DEV_US_PORT;
else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
edev->mode |= EEH_DEV_DS_PORT;
}
When fixing AER registers on PowerNV platform, we need the position of AER capability for each PCI device. The patch caches that to EEH device during probe time. Also, the patch figures the EEH device is associated with the upstream port of PCIe bridge or not, which is useful while fixing AER registers on PowerNV platform. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> --- arch/powerpc/include/asm/eeh.h | 8 +++++--- arch/powerpc/platforms/powernv/eeh-powernv.c | 5 ++++- 2 files changed, 9 insertions(+), 4 deletions(-)