diff mbox

target-arm: aarch64: ask for suggestion, a few insn implementations for review.

Message ID CAF1ZMEfH1hs0V675kPxprX=79LZfeixRSrz8RTvJwL1cDYcUUA@mail.gmail.com
State New
Headers show

Commit Message

Dennis Lan (dlan) Dec. 23, 2013, 8:13 a.m. UTC 
On Mon, Dec 23, 2013 at 4:09 PM, Dennis Lan (dlan)
<dennis.yxun@gmail.com> wrote:
> Hi Folks:
>    I'm writing this letter mainly for help and suggestion.
>    I'm using qemu-aarch64[1] from matz's repository, which actually is
> not official.
> with matz's repo, and trying to build a small gentoo rootfs, I
> encountered a problem with gcc-4.9.0 and if only commit[2] is
> included, I have reported to gcc upstream, for more information can be
> found here[3]
>
>    The problem is that there are still a few insn implementations
> missing in matz's repo,
> so I try to implement them myself[4]. I'm not familiar with qemu tcg,
> so those patches probably more than a hack, it would be great if
> anyone can help to review, whether I'm doing this correct or not (I'm
> not seeking for upstreaming those patches).
>    yes, I've seen aarch64's work is heading for upstream, and I jumped
> a little ahead..
> so, let me know what the best i can do.
>
> Lan
>
> [1] git://github.com/susematz/qemu.git , branch: aarch64-1.6
>
> [2] commit from gcc-4.9.0
> commit 07ca5686e64d32f7df4ccf4205d0b914f120da5e
> Author: yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4>
> Date:   Thu Sep 26 09:09:30 2013 +0000
>
>     2013-09-26  Yvan Roux  <yvan.roux@linaro.org>
>
>         * config/aarch64/aarch64.opt (mlra): New option.
>         * config/aarch64/aarch64.c (aarch64_lra_p): New function.
>         (TARGET_LRA_P): Define.
>
>     git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202940
> 138bc75d-0d04-0410-961f-82ee72b054a4
>
> [3] http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59573
>
> [4] aarch64 patches
>  git://github.com/dlanx/qemu.git , branch: aarch64-1.6
>
>       aarch64: Implement simd SHL immediate support
>       aarch64: Enable NEG insn support which is already implemented
>       aarch64: Enable USHL insn support which is already implemented
>       aarch64: Implement CMEQ(zero) scalar insn

Intead of use "git send-email", I just paste patches here
let me know if I did this wrong.


From b0703396ac634e9f28ae3bec63f123e95136257d Mon Sep 17 00:00:00 2001
From: "Lan Yixun (dlan)" <dennis.yxun@gmail.com>
Date: Tue, 10 Dec 2013 19:08:52 +0800
Subject: [PATCH 1/4] aarch64: Implement simd SHL immediate support

C6.3.222 SHL scalar variant instruction

Signed-off-by: Lan Yixun (dlan) <dennis.yxun@gmail.com>
---
 target-arm/translate-a64.c | 5 +++++
 1 file changed, 5 insertions(+)

     unallocated_encoding(s);

Comments

Peter Maydell Jan. 27, 2014, 6:15 p.m. UTC | #1 
On 23 December 2013 08:13, Dennis Lan (dlan) <dennis.yxun@gmail.com> wrote:
> On Mon, Dec 23, 2013 at 4:09 PM, Dennis Lan (dlan)
> <dennis.yxun@gmail.com> wrote:
>>    The problem is that there are still a few insn implementations
>> missing in matz's repo,
>> so I try to implement them myself[4]. I'm not familiar with qemu tcg,
>> so those patches probably more than a hack, it would be great if
>> anyone can help to review, whether I'm doing this correct or not (I'm
>> not seeking for upstreaming those patches).
>>    yes, I've seen aarch64's work is heading for upstream, and I jumped
>> a little ahead..

Thanks. I think we now have implementations of all these:

> C6.3.222 SHL scalar variant instruction
> C6.3.184 NEG scalar variant instruction
> C6.3.338 USHL scalar variant instruction
> C6.3.20 CMEQ(zero) scalar

in the most recent set of patches for A64 neon support
I posted yesterday.

thanks
-- PMM
diff mbox

Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 36ebb0f..88cc2dc 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3617,6 +3617,7 @@  static void handle_simd_shifti(DisasContext *s,
uint32_t insn)
     int opcode = get_bits(insn, 11, 5);
     int immb = get_bits(insn, 16, 3);
     int immh = get_bits(insn, 19, 4);
+    bool is_scalar = get_bits(insn, 28, 1);
     bool is_u = get_bits(insn, 29, 1);
     bool is_q = get_bits(insn, 30, 1);
     bool accumulate = get_bits(insn, 12, 1);
@@ -3658,6 +3659,7 @@  static void handle_simd_shifti(DisasContext *s,
uint32_t insn)
         unallocated_encoding(s);
         return;
     }
+    if (is_scalar) is_q = false;
     accumulate = round = false;
     shift = shift - (8 << size);
     break;
@@ -4474,6 +4476,9 @@  void disas_a64_insn(CPUARMState *env, DisasContext *s)
             handle_fpdp3s32(s, insn);
         } else if (!get_bits(insn, 29, 3) && (get_bits(insn, 22, 2) == 0x1)) {
             handle_fpdp3s64(s, insn);
+        } else if (!get_bits(insn, 31, 1) && !get_bits(insn, 23, 1) &&
+            get_bits(insn, 10, 1) && (get_bits(insn, 11, 5) == 0xA)) {
+            handle_simd_shifti(s, insn);
         } else {
             goto unknown_insn;
         }
-- 
1.8.5.2

From 240b63309c0f8f8f91282bfd461c6cb786c4b0c2 Mon Sep 17 00:00:00 2001
From: "Lan Yixun (dlan)" <dennis.yxun@gmail.com>
Date: Fri, 13 Dec 2013 21:39:59 +0800
Subject: [PATCH 2/4] aarch64: Enable NEG insn support which is already
 implemented

C6.3.184 NEG scalar variant instruction

Signed-off-by: Lan Yixun (dlan) <dennis.yxun@gmail.com>
---
 target-arm/translate-a64.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 88cc2dc..1a816ae 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -4467,6 +4467,9 @@  void disas_a64_insn(CPUARMState *env, DisasContext *s)
         } else {
         handle_scpsp (s, insn);
         }
+        } else if (get_bits(insn, 17, 5) == 0x10 &&
+                   get_bits(insn, 11, 1) && !get_bits(insn, 10, 1)) {
+            handle_simd_misc(s, insn);
         } else {
             goto unknown_insn;
         }
-- 
1.8.5.2

From e1afeb63120acec26f95e5b229c2340c0cba794a Mon Sep 17 00:00:00 2001
From: "Lan Yixun (dlan)" <dennis.yxun@gmail.com>
Date: Fri, 13 Dec 2013 22:35:40 +0800
Subject: [PATCH 3/4] aarch64: Enable USHL insn support which is already
 implemented

C6.3.338 USHL scalar variant instruction

Signed-off-by: Lan Yixun (dlan) <dennis.yxun@gmail.com>
---
 target-arm/translate-a64.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 1a816ae..8b2570a 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2839,6 +2839,7 @@  static void handle_simd3s(DisasContext *s, uint32_t insn)
     int opcode = get_bits(insn, 11, 5);
     bool is_q = get_bits(insn, 30, 1);
     bool is_u = get_bits(insn, 29, 1);
+    bool is_scalar = get_bits(insn, 28, 1);
     bool is_pair = is_u;
     bool is_float = false;
     bool is_op2 = false;
@@ -2893,6 +2894,8 @@  static void handle_simd3s(DisasContext *s, uint32_t insn)
         unallocated_encoding(s);
         return;
     }
+    case 0x08: /* USHL */
+    if (is_scalar) is_q = false;
     break;
     }

@@ -4470,6 +4473,8 @@  void disas_a64_insn(CPUARMState *env, DisasContext *s)
         } else if (get_bits(insn, 17, 5) == 0x10 &&
                    get_bits(insn, 11, 1) && !get_bits(insn, 10, 1)) {
             handle_simd_misc(s, insn);
+        } else if (get_bits(insn, 21, 1) && get_bits(insn, 10, 1)) {
+          handle_simd3s(s, insn);
         } else {
             goto unknown_insn;
         }
-- 
1.8.5.2

From 1a9b3a40917c416125f10accba9e531ed91677d4 Mon Sep 17 00:00:00 2001
From: "Lan Yixun (dlan)" <dennis.yxun@gmail.com>
Date: Tue, 17 Dec 2013 13:30:02 +0800
Subject: [PATCH 4/4] aarch64: Implement CMEQ(zero) scalar insn

C6.3.20 CMEQ(zero) scalar

Signed-off-by: Lan Yixun (dlan) <dennis.yxun@gmail.com>
---
 target-arm/translate-a64.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 8b2570a..d0470af 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3460,6 +3460,20 @@  static void handle_simd_misc(DisasContext *s,
uint32_t insn)
           tcg_temp_free_i64(zero);
       }
     }
+    case 0x09: /* CMEQ */
+    {
+      bool is_scalar = get_bits(insn, 28, 1);
+          TCGv_i64 tcg_zero = tcg_const_i64(0);
+      if (is_scalar) {
+          if (size != 3) {
+          unallocated_encoding(s);
+          return;
+          }
+              tcg_gen_setcond_i64 (TCG_COND_NE, tcg_res, tcg_op1, tcg_zero);
+              tcg_gen_subi_i64 (tcg_res, tcg_res, 1);
+              simd_st(tcg_res, freg_offs_d, 3);
+      }
+        }
     break;
     default: