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[v2,5/9] target-sh4: optimize negc using add2 and sub2

Message ID 1387713039-9584-6-git-send-email-aurelien@aurel32.net
State New
Headers show

Commit Message

Aurelien Jarno Dec. 22, 2013, 11:50 a.m. UTC 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/translate.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Richard Henderson Dec. 24, 2013, 2:25 p.m. UTC | #1 
On 12/22/2013 03:50 AM, Aurelien Jarno wrote:
> +            TCGv t0 = tcg_const_i32(0);
> +            tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
> +                             REG(B7_4), t0, cpu_sr_t, t0);
> +            tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
> +                             t0, t0, REG(B11_8), cpu_sr_t);

While this formulation is correct, I wonder why you strayed from the two
subtracts model of subc, since negc is similarly described in the manual?

Otherwise,

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
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Patch

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 21605b0..4ef0398 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -797,12 +797,12 @@  static void _decode_opc(DisasContext * ctx)
 	return;
     case 0x600a:		/* negc Rm,Rn */
         {
-            TCGv t0 = tcg_temp_new();
-            tcg_gen_neg_i32(t0, REG(B7_4));
-            tcg_gen_sub_i32(REG(B11_8), t0, cpu_sr_t);
-            tcg_gen_setcondi_i32(TCG_COND_GTU, cpu_sr_t, t0, 0);
-            tcg_gen_setcond_i32(TCG_COND_GTU, t0, REG(B11_8), t0);
-            tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0);
+            TCGv t0 = tcg_const_i32(0);
+            tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
+                             REG(B7_4), t0, cpu_sr_t, t0);
+            tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
+                             t0, t0, REG(B11_8), cpu_sr_t);
+            tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
             tcg_temp_free(t0);
         }
 	return;