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+* APM X-Gene SOC Queue Manager/Traffic Manager nodes
+
+QMTM nodes are defined to describe on-chip Queue Managers in APM X-Gene SOC.
+APM X-Gene SOC Ethernet, PktDMA, and Security Engine subsystems communicate
+with a central Queue Manager using messages which include information about
+the work to be performed and the location of the associated data buffers.
+There are multiple instances of QMTM. Each QMTM instance has its own node.
+Its corresponding clock nodes are shown below.
+
+Required properties:
+- compatible : Shall be "apm,xgene-qmtm-lite" for QMLite instance
+- reg : First memory resource shall be the QMTM CSR memory
+ resource.
+ Second memory resource shall be the QMTM IO-Fabric
+ memory resource.
+- slave-name : Shall be "CPU_QMTM3" which is receiver for ingress
+ work messages for the QMTM. Here receiver is CPU.
+- interrupts : First interrupt resource shall be the QMTM Error
+ interrupt.
+ Remaining interrupt resources shall be the Ingress
+ work message interrupt mapping for receiver,
+ receiving work messages for the QMTM.
+- clocks : Reference to the clock entry.
+
+Optional properties:
+- status : Shall be "ok" if enabled or "disabled" if disabled.
+ Default is "ok".
+
+Example:
+ qmlclk: qmlclk {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clock-names = "qmlclk";
+ status = "ok";
+ csr-offset = <0x0>;
+ csr-mask = <0x3>;
+ enable-offset = <0x8>;
+ enable-mask = <0x3>;
+ };
+
+ qmlite: qmtm@17030000 {
+ compatible = "apm,xgene-qmtm-lite";
+ reg = <0x0 0x17030000 0x0 0x10000>,
+ <0x0 0x10000000 0x0 0x400000>;
+ slave-name = "CPU_QMTM3";
+ interrupts = <0x0 0x40 0x4>,
+ <0x0 0x3c 0x4>;
+ status = "ok";
+ #clock-cells = <1>;
+ clocks = <&qmlclk 0>;
+ };