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[129.42.161.36]) by mx.google.com with ESMTPSA id si9sm1901466oeb.8.2013.12.18.12.49.18 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Dec 2013 12:49:19 -0800 (PST) From: Tom Musta To: qemu-devel@nongnu.org Date: Wed, 18 Dec 2013 14:48:54 -0600 Message-Id: <1387399747-4994-2-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387399747-4994-1-git-send-email-tommusta@gmail.com> References: <1387399747-4994-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c02::235 Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V3 PATCH 01/14] target-ppc: Add Flag for Power ISA V2.06 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds a flag for base instruction additions to Power ISA 2.06B. The flag will be used to identify/select basic Book I and Book II instructions that were newly added in that revision of the architecture. The flag will not be used for VSX or Altivec. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- target-ppc/cpu.h | 4 +++- target-ppc/translate_init.c | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 0abc848..fe3aace 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1877,9 +1877,11 @@ enum { PPC2_ISA205 = 0x0000000000000020ULL, /* VSX additions in ISA 2.07 */ PPC2_VSX207 = 0x0000000000000040ULL, + /* Book I 2.06B PowerPC specification (base instructions) */ + PPC2_ISA206 = 0x0000000000000080ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ - PPC2_ISA205 | PPC2_VSX207) + PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index e14ab63..491e56c 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205; + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | + PPC2_ISA206; pcc->msr_mask = 0x800000000284FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_ISA206; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU)