Patchwork [V4,18/22] target-ppc: Add VSX xmax/xmin Instructions

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Submitter Tom Musta
Date Dec. 18, 2013, 8:19 p.m.
Message ID <1387397961-4894-19-git-send-email-tommusta@gmail.com>
Download mbox | patch
Permalink /patch/303051/
State New
Headers show

Comments

Tom Musta - Dec. 18, 2013, 8:19 p.m.
This patch adds the VSX floating point maximum and minimum
instructions:

  - xsmaxdp, xvmaxdp, xvmaxsp
  - xsmindp, xvmindp, xvminsp

Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison
routines (e.g. float64_lt) do not work as well as one might
think.  Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.

V2: consolidated into a single macro, using the softfloat
float*_max/float*_min routines.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <address@hidden>
---
 target-ppc/fpu_helper.c |   50 +++++++++++++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h     |    6 +++++
 target-ppc/translate.c  |   12 +++++++++++
 3 files changed, 68 insertions(+), 0 deletions(-)
Richard Henderson - Dec. 24, 2013, 4:23 p.m.
On 12/18/2013 12:19 PM, Tom Musta wrote:
> +        if (unlikely(tp##_is_any_nan(xa.fld[i]) ||                            \
> +                     tp##_is_any_nan(xb.fld[i]))) {                           \
> +            if (tp##_is_signaling_nan(xa.fld[i])) {                           \
> +                xt.fld[i] = tp##_snan_to_qnan(xa.fld[i]);                     \
> +                fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);        \
> +            } else if (tp##_is_signaling_nan(xb.fld[i])) {                    \
> +                xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]);                     \
> +                fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);        \
> +            } else if (tp##_is_quiet_nan(xb.fld[i])) {                        \
> +                xt.fld[i] = xa.fld[i];                                        \
> +            } else { /* XA is QNaN */                                         \
> +                xt.fld[i] = xb.fld[i];                                        \
> +            }                                                                 \
> +        } else {                                                              \
> +            xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &env->fp_status);     \
> +        }                                                                     \

We have minnum/maxnum now.


r~

Patch

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index eb5d878..b90541c 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2288,3 +2288,53 @@  void helper_##op(CPUPPCState *env, uint32_t opcode)                      \
 
 VSX_SCALAR_CMP(xscmpodp, 1)
 VSX_SCALAR_CMP(xscmpudp, 0)
+
+#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ul)
+#define float32_snan_to_qnan(x) ((x) | 0x00400000)
+
+/* VSX_MAX_MIN - VSX floating point maximum/minimum
+ *   name  - instruction mnemonic
+ *   op    - operation (max or min)
+ *   nels  - number of elements (1, 2 or 4)
+ *   tp    - type (float32 or float64)
+ *   fld   - vsr_t field (f32 or f64)
+ */
+#define VSX_MAX_MIN(name, op, nels, tp, fld)                                  \
+void helper_##name(CPUPPCState *env, uint32_t opcode)                         \
+{                                                                             \
+    ppc_vsr_t xt, xa, xb;                                                     \
+    int i;                                                                    \
+                                                                              \
+    getVSR(xA(opcode), &xa, env);                                             \
+    getVSR(xB(opcode), &xb, env);                                             \
+    getVSR(xT(opcode), &xt, env);                                             \
+                                                                              \
+    for (i = 0; i < nels; i++) {                                              \
+        if (unlikely(tp##_is_any_nan(xa.fld[i]) ||                            \
+                     tp##_is_any_nan(xb.fld[i]))) {                           \
+            if (tp##_is_signaling_nan(xa.fld[i])) {                           \
+                xt.fld[i] = tp##_snan_to_qnan(xa.fld[i]);                     \
+                fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);        \
+            } else if (tp##_is_signaling_nan(xb.fld[i])) {                    \
+                xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]);                     \
+                fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);        \
+            } else if (tp##_is_quiet_nan(xb.fld[i])) {                        \
+                xt.fld[i] = xa.fld[i];                                        \
+            } else { /* XA is QNaN */                                         \
+                xt.fld[i] = xb.fld[i];                                        \
+            }                                                                 \
+        } else {                                                              \
+            xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &env->fp_status);     \
+        }                                                                     \
+    }                                                                         \
+                                                                              \
+    putVSR(xT(opcode), &xt, env);                                             \
+    helper_float_check_status(env);                                           \
+}
+
+VSX_MAX_MIN(xsmaxdp, max, 1, float64, f64)
+VSX_MAX_MIN(xvmaxdp, max, 2, float64, f64)
+VSX_MAX_MIN(xvmaxsp, max, 4, float32, f32)
+VSX_MAX_MIN(xsmindp, min, 1, float64, f64)
+VSX_MAX_MIN(xvmindp, min, 2, float64, f64)
+VSX_MAX_MIN(xvminsp, min, 4, float32, f32)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index cd72388..4a65d39 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -270,6 +270,8 @@  DEF_HELPER_2(xsnmsubadp, void, env, i32)
 DEF_HELPER_2(xsnmsubmdp, void, env, i32)
 DEF_HELPER_2(xscmpodp, void, env, i32)
 DEF_HELPER_2(xscmpudp, void, env, i32)
+DEF_HELPER_2(xsmaxdp, void, env, i32)
+DEF_HELPER_2(xsmindp, void, env, i32)
 
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -288,6 +290,8 @@  DEF_HELPER_2(xvnmaddadp, void, env, i32)
 DEF_HELPER_2(xvnmaddmdp, void, env, i32)
 DEF_HELPER_2(xvnmsubadp, void, env, i32)
 DEF_HELPER_2(xvnmsubmdp, void, env, i32)
+DEF_HELPER_2(xvmaxdp, void, env, i32)
+DEF_HELPER_2(xvmindp, void, env, i32)
 
 DEF_HELPER_2(xvaddsp, void, env, i32)
 DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -306,6 +310,8 @@  DEF_HELPER_2(xvnmaddasp, void, env, i32)
 DEF_HELPER_2(xvnmaddmsp, void, env, i32)
 DEF_HELPER_2(xvnmsubasp, void, env, i32)
 DEF_HELPER_2(xvnmsubmsp, void, env, i32)
+DEF_HELPER_2(xvmaxsp, void, env, i32)
+DEF_HELPER_2(xvminsp, void, env, i32)
 
 DEF_HELPER_2(efscfsi, i32, env, i32)
 DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a2a4e2d..10c238a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7314,6 +7314,8 @@  GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
 
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -7332,6 +7334,8 @@  GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
 
 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
@@ -7350,6 +7354,8 @@  GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
 
 #define VSX_LOGICAL(name, tcg_op)                                    \
 static void glue(gen_, name)(DisasContext * ctx)                     \
@@ -10052,6 +10058,8 @@  GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
 GEN_XX2FORM(xscmpodp,  0x0C, 0x05, PPC2_VSX),
 GEN_XX2FORM(xscmpudp,  0x0C, 0x04, PPC2_VSX),
+GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
+GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
 
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
@@ -10070,6 +10078,8 @@  GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
+GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
 
 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
@@ -10088,6 +10098,8 @@  GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
+GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
 
 #undef VSX_LOGICAL
 #define VSX_LOGICAL(name, opc2, opc3, fl2) \