diff mbox

[AArch64,3/6] Implement support for Crypto -- AES.

Message ID 52B1BF16.6030302@arm.com
State New
Headers show

Commit Message

Tejas Belagod Dec. 18, 2013, 3:28 p.m. UTC 
Marcus Shawcroft wrote:
> On 6 December 2013 17:36, Tejas Belagod <tbelagod@arm.com> wrote:
> 
>>         * gcc.target/aarch64/aes.c: New.
> 
> Add _1 on the test case file name (see http://gcc.gnu.org/wiki/TestCaseWriting)
> 
> 
>> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
>> index dc56170..9f35e09 100644
>> --- a/gcc/config/aarch64/arm_neon.h
>> +++ b/gcc/config/aarch64/arm_neon.h
>> @@ -15793,6 +15793,42 @@ vaddvq_f64 (float64x2_t __a)
>>    return vgetq_lane_f64 (__t, __LANE0 (2));
>>  }
>>
>> +#ifdef __ARM_FEATURE_CRYPTO
>> +
>> +/* vaes  */
>> +
>> +static __inline uint8x16_t
>> +vaeseq_u8 (uint8x16_t data, uint8x16_t key)
>> +{
>> +  return
>> +    (uint8x16_t) __builtin_aarch64_crypto_aesev16qi ((int8x16_t) data,
>> +                                                    (int8x16_t) key);
> 
> James G fixed the infrastructure to allow properly typed builtins, see:
> 
> http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02005.html
> and
> http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02880.html
> 
> 
>> @@ -959,3 +966,7 @@
>>                             (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
>>
>>  (define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
>> +
>> +(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
>> +(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
>> +
> 
> Superflous trailing blank line.
> 
>> diff --git a/gcc/testsuite/gcc.target/aarch64/aes.c
>> b/gcc/testsuite/gcc.target/aarch64/aes.c
>> new file mode 100644
>> index 0000000..82665fa
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/aes.c
>> @@ -0,0 +1,40 @@
>> +
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=armv8-a+crypto" } */
>> +
>> +#include "arm_neon.h"
>> +
>> +uint8x16_t
>> +test_vaeseq_u8 (uint8x16_t data, uint8x16_t key)
>> +{
>> +  return vaeseq_u8 (data, key);
>> +}
>> +
>> +/* { dg-final { scan-assembler "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" } }
> 
> Use scan-assembler-times 1 instead please.

Thanks for the review. Here is an improved patch.

Tested on aarch64-none-elf. OK for trunk?

Thanks
Tejas.

2013-12-18  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
	* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
	TYPES_BINOPU): New.
	* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
	aarch64_crypto_aes<aesmc_op>v16qi): New.
	* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
	vaesimcq_u8): New.
	* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
	UNSPEC_AESIMC): New.
	(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
	(aes_op, aesmc_op): New int attributes.

testsuite/
	* gcc.target/aarch64/aes_1.c: New.

Comments

Marcus Shawcroft Dec. 18, 2013, 6:26 p.m. UTC | #1 
On 18 December 2013 15:28, Tejas Belagod <tbelagod@arm.com> wrote:

> 2013-12-18  Tejas Belagod  <tejas.belagod@arm.com>
>
>
> gcc/
>         * config/aarch64/aarch64-simd-builtins.def: Update builtins table.
>         * config/aarch64/aarch64-builtins.c
> (aarch64_types_binopu_qualifiers,
>         TYPES_BINOPU): New.
>
>         * config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
>         aarch64_crypto_aes<aesmc_op>v16qi): New.
>         * config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
>         vaesimcq_u8): New.
>         * config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD,
> UNSPEC_AESMC,
>         UNSPEC_AESIMC): New.
>         (CRYPTO_AES, CRYPTO_AESMC): New int iterators.
>         (aes_op, aesmc_op): New int attributes.
>
> testsuite/
>         * gcc.target/aarch64/aes_1.c: New.

OK, Thanks /Marcus
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 1bc3cc5..00a33ce 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -142,6 +142,10 @@  static enum aarch64_type_qualifiers
 aarch64_types_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none };
 #define TYPES_UNOP (aarch64_types_unop_qualifiers)
+static enum aarch64_type_qualifiers
+aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_unsigned };
+#define TYPES_UNOPU (aarch64_types_unopu_qualifiers)
 #define TYPES_CREATE (aarch64_types_unop_qualifiers)
 #define TYPES_REINTERP (aarch64_types_unop_qualifiers)
 static enum aarch64_type_qualifiers
@@ -149,6 +153,10 @@  aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_maybe_immediate };
 #define TYPES_BINOP (aarch64_types_binop_qualifiers)
 static enum aarch64_type_qualifiers
+aarch64_types_binopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned };
+#define TYPES_BINOPU (aarch64_types_binopu_qualifiers)
+static enum aarch64_type_qualifiers
 aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
 #define TYPES_TERNOP (aarch64_types_ternop_qualifiers)
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 1dc3c1f..6b72e8f 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -367,3 +367,8 @@ 
   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 
+  /* Implemented by aarch64_crypto_aes<op><mode>.  */
+  VAR1 (BINOPU, crypto_aese, 0, v16qi)
+  VAR1 (BINOPU, crypto_aesd, 0, v16qi)
+  VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
+  VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 158b3dc..f8c204f 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4074,3 +4074,25 @@ 
       (gen_aarch64_get_lane<mode> (operands[0], operands[1], operands[2]));
     DONE;
 })
+
+;; aes
+
+(define_insn "aarch64_crypto_aes<aes_op>v16qi"
+  [(set (match_operand:V16QI 0 "register_operand" "=w")
+        (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
+		       (match_operand:V16QI 2 "register_operand" "w")]
+         CRYPTO_AES))]
+  "TARGET_SIMD && TARGET_CRYPTO"
+  "aes<aes_op>\\t%0.16b, %2.16b"
+  [(set_attr "type" "crypto_aes")]
+)
+
+(define_insn "aarch64_crypto_aes<aesmc_op>v16qi"
+  [(set (match_operand:V16QI 0 "register_operand" "=w")
+	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "w")]
+	 CRYPTO_AESMC))]
+  "TARGET_SIMD && TARGET_CRYPTO"
+  "aes<aesmc_op>\\t%0.16b, %1.16b"
+  [(set_attr "type" "crypto_aes")]
+)
+
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 03549bd..6cfea43 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -15575,6 +15575,36 @@  vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
   return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
 }
 
+#ifdef __ARM_FEATURE_CRYPTO
+
+/* vaes  */
+
+static __inline uint8x16_t
+vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return __builtin_aarch64_crypto_aesev16qi_uuu (data, key);
+}
+
+static __inline uint8x16_t
+vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return __builtin_aarch64_crypto_aesdv16qi_uuu (data, key);
+}
+
+static __inline uint8x16_t
+vaesmcq_u8 (uint8x16_t data)
+{
+  return __builtin_aarch64_crypto_aesmcv16qi_uu (data);
+}
+
+static __inline uint8x16_t
+vaesimcq_u8 (uint8x16_t data)
+{
+  return __builtin_aarch64_crypto_aesimcv16qi_uu (data);
+}
+
+#endif
+
 /* vcage  */
 
 __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 43279ad..eeab8e9 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -267,6 +267,10 @@ 
     UNSPEC_UZP2		; Used in vector permute patterns.
     UNSPEC_TRN1		; Used in vector permute patterns.
     UNSPEC_TRN2		; Used in vector permute patterns.
+    UNSPEC_AESE		; Used in aarch64-simd.md.
+    UNSPEC_AESD         ; Used in aarch64-simd.md.
+    UNSPEC_AESMC        ; Used in aarch64-simd.md.
+    UNSPEC_AESIMC       ; Used in aarch64-simd.md.
 ])
 
 ;; -------------------------------------------------------------------
@@ -848,6 +852,9 @@ 
 
 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
 
+(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
+(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
+
 ;; -------------------------------------------------------------------
 ;; Int Iterators Attributes.
 ;; -------------------------------------------------------------------
@@ -964,3 +971,6 @@ 
 			    (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
 
 (define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
+
+(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
+(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
diff --git a/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc/testsuite/gcc.target/aarch64/aes_1.c
new file mode 100644
index 0000000..5fa6137
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/aes_1.c
@@ -0,0 +1,40 @@ 
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint8x16_t
+test_vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return vaeseq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return vaesdq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aesd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesmcq_u8 (uint8x16_t data)
+{
+  return vaesmcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesmc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesimcq_u8 (uint8x16_t data)
+{
+  return vaesimcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesimc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */