From patchwork Tue Dec 17 20:28:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 302552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E3CE52C00AE for ; Wed, 18 Dec 2013 09:33:54 +1100 (EST) Received: from localhost ([::1]:35559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1yv-0002vv-Tc for incoming@patchwork.ozlabs.org; Tue, 17 Dec 2013 16:15:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1hG-000171-BL for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:56:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vt1hE-0002SE-41 for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:56:53 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43647) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1hD-0002SA-TQ for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:56:52 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Vt1Gd-0003Hh-0T; Tue, 17 Dec 2013 20:29:23 +0000 From: Peter Maydell To: Anthony Liguori Date: Tue, 17 Dec 2013 20:28:55 +0000 Message-Id: <1387312160-12318-38-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> References: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Graf This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 1d04303..5ae3a85 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -202,6 +202,25 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg) } } +/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 + * representing the register contents. This TCGv is an auto-freed + * temporary so it need not be explicitly freed, and may be modified. + */ +static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) +{ + TCGv_i64 v = new_tmp_a64(s); + if (reg != 31) { + if (sf) { + tcg_gen_mov_i64(v, cpu_X[reg]); + } else { + tcg_gen_ext32u_i64(v, cpu_X[reg]); + } + } else { + tcg_gen_movi_i64(v, 0); + } + return v; +} + /* * the instruction disassembly implemented here matches * the instruction encoding classifications in chapter 3 (C3) @@ -227,10 +246,33 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) gen_goto_tb(s, 0, addr); } -/* Compare & branch (immediate) */ +/* C3.2.1 Compare & branch (immediate) + * 31 30 25 24 23 5 4 0 + * +----+-------------+----+---------------------+--------+ + * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | + * +----+-------------+----+---------------------+--------+ + */ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, op, rt; + uint64_t addr; + int label_match; + TCGv_i64 tcg_cmp; + + sf = extract32(insn, 31, 1); + op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ + rt = extract32(insn, 0, 5); + addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; + + tcg_cmp = read_cpu_reg(s, rt, sf); + label_match = gen_new_label(); + + tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_cmp, 0, label_match); + + gen_goto_tb(s, 0, s->pc); + gen_set_label(label_match); + gen_goto_tb(s, 1, addr); } /* C3.2.5 Test & branch (immediate)