diff mbox

[15/21] target-arm: Widen thread-local register state fields to 64 bits

Message ID 1387293144-11554-16-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell Dec. 17, 2013, 3:12 p.m. UTC 
The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a view of the
bottom 32 bits of the 64-bit AArch64 system register; writes in
AArch32 leave the top half unchanged. The most natural way to
model this is to have the state field in the CPU struct be a
64 bit value, and simply have the AArch32 TCG code operate on
a pointer to its lower half.

For aarch64-linux-user the only registers we need to share like
this are the thread-local-storage ones. Widen their fields to
64 bits and provide the 64 bit reginfo struct to make them
visible in AArch64 state.

Since we're touching almost every line in QEMU that uses the
c13_tls* fields in this patch anyway, we take the opportunity
to rename them in line with the standard ARM architectural names
for these registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/target_cpu.h |  5 ++++-
 linux-user/arm/target_cpu.h     |  2 +-
 linux-user/main.c               |  2 +-
 target-arm/cpu.h                | 18 +++++++++++++++---
 target-arm/helper.c             | 15 ++++++++++++---
 5 files changed, 33 insertions(+), 9 deletions(-)

Comments

Richard Henderson Dec. 19, 2013, 8:53 p.m. UTC | #1 
On 12/17/2013 07:12 AM, Peter Maydell wrote:
> -        uint32_t c13_tls1; /* User RW Thread register.  */
> -        uint32_t c13_tls2; /* User RO Thread register.  */
> -        uint32_t c13_tls3; /* Privileged Thread register.  */
> +        uint64_t tpidr_el0; /* User RW Thread register.  */
> +        uint64_t tpidrro_el0; /* User RO Thread register.  */
> +        uint64_t tpidr_el1; /* Privileged Thread register.  */

Not target_ulong, continuing to use 32bit slot for pure AA32?


r~
Peter Maydell Dec. 19, 2013, 9:04 p.m. UTC | #2 
On 19 December 2013 20:53, Richard Henderson <rth@twiddle.net> wrote:
> On 12/17/2013 07:12 AM, Peter Maydell wrote:
>> -        uint32_t c13_tls1; /* User RW Thread register.  */
>> -        uint32_t c13_tls2; /* User RO Thread register.  */
>> -        uint32_t c13_tls3; /* Privileged Thread register.  */
>> +        uint64_t tpidr_el0; /* User RW Thread register.  */
>> +        uint64_t tpidrro_el0; /* User RO Thread register.  */
>> +        uint64_t tpidr_el1; /* Privileged Thread register.  */
>
> Not target_ulong, continuing to use 32bit slot for pure AA32?

It would only be a 32 bit slot for the 32 bit cores in qemu-arm;
the same cores in qemu-aarch64 would be 64 bits. I think
I'd rather have the consistency (and the ability to migrate
between a qemu-arm cortex-a9 and a qemu-aarch64 cortex-a9
doesn't hurt).

thanks
-- PMM
Richard Henderson Dec. 19, 2013, 9:09 p.m. UTC | #3 
On 12/19/2013 01:04 PM, Peter Maydell wrote:
> On 19 December 2013 20:53, Richard Henderson <rth@twiddle.net> wrote:
>> On 12/17/2013 07:12 AM, Peter Maydell wrote:
>>> -        uint32_t c13_tls1; /* User RW Thread register.  */
>>> -        uint32_t c13_tls2; /* User RO Thread register.  */
>>> -        uint32_t c13_tls3; /* Privileged Thread register.  */
>>> +        uint64_t tpidr_el0; /* User RW Thread register.  */
>>> +        uint64_t tpidrro_el0; /* User RO Thread register.  */
>>> +        uint64_t tpidr_el1; /* Privileged Thread register.  */
>>
>> Not target_ulong, continuing to use 32bit slot for pure AA32?
> 
> It would only be a 32 bit slot for the 32 bit cores in qemu-arm;
> the same cores in qemu-aarch64 would be 64 bits. I think
> I'd rather have the consistency (and the ability to migrate
> between a qemu-arm cortex-a9 and a qemu-aarch64 cortex-a9
> doesn't hurt).

Fair enough.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
index 6f5539b..21560ef 100644
--- a/linux-user/aarch64/target_cpu.h
+++ b/linux-user/aarch64/target_cpu.h
@@ -29,7 +29,10 @@  static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 
 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 {
-    env->sr.tpidr_el0 = newtls;
+    /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
+     * different from AArch32 Linux, which uses TPIDRRO.
+     */
+    env->cp15.tpidr_el0 = newtls;
 }
 
 #endif
diff --git a/linux-user/arm/target_cpu.h b/linux-user/arm/target_cpu.h
index ed323c0..39d65b6 100644
--- a/linux-user/arm/target_cpu.h
+++ b/linux-user/arm/target_cpu.h
@@ -29,7 +29,7 @@  static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 
 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 {
-    env->cp15.c13_tls2 = newtls;
+    env->cp15.tpidrro_el0 = newtls;
 }
 
 #endif
diff --git a/linux-user/main.c b/linux-user/main.c
index 54f71fe..c0df8b5 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -566,7 +566,7 @@  do_kernel_trap(CPUARMState *env)
         end_exclusive();
         break;
     case 0xffff0fe0: /* __kernel_get_tls */
-        env->regs[0] = env->cp15.c13_tls2;
+        env->regs[0] = env->cp15.tpidrro_el0;
         break;
     case 0xffff0f60: /* __kernel_cmpxchg64 */
         arm_kernel_cmpxchg64_helper(env);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 32387b0..81c0b1c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -66,6 +66,18 @@ 
 /* ARM-specific interrupt pending bits.  */
 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
 
+/* The usual mapping for an AArch64 system register to its AArch32
+ * counterpart is for the 32 bit world to have access to the lower
+ * half only (with writes leaving the upper half untouched). It's
+ * therefore useful to be able to pass TCG the offset of the least
+ * significant half of a uint64_t struct member.
+ */
+#ifdef HOST_WORDS_BIGENDIAN
+#define offsetoflow32(S, M) (offsetof(S, M + sizeof(uint32_t))
+#else
+#define offsetoflow32(S, M) offsetof(S, M)
+#endif
+
 /* Meanings of the ARMCPU object's two inbound GPIO lines */
 #define ARM_CPU_IRQ 0
 #define ARM_CPU_FIQ 1
@@ -188,9 +200,9 @@  typedef struct CPUARMState {
         uint32_t c12_vbar; /* vector base address register */
         uint32_t c13_fcse; /* FCSE PID.  */
         uint32_t c13_context; /* Context ID.  */
-        uint32_t c13_tls1; /* User RW Thread register.  */
-        uint32_t c13_tls2; /* User RO Thread register.  */
-        uint32_t c13_tls3; /* Privileged Thread register.  */
+        uint64_t tpidr_el0; /* User RW Thread register.  */
+        uint64_t tpidrro_el0; /* User RO Thread register.  */
+        uint64_t tpidr_el1; /* Privileged Thread register.  */
         uint32_t c14_cntfrq; /* Counter Frequency register */
         uint32_t c14_cntkctl; /* Timer Control register */
         ARMGenericTimer c14_timer[NUM_GTIMERS];
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c64f618..0754058 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -742,15 +742,15 @@  static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 static const ARMCPRegInfo v6k_cp_reginfo[] = {
     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW,
-      .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
+      .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
       .resetvalue = 0 },
     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
       .access = PL0_R|PL1_W,
-      .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
+      .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
       .resetvalue = 0 },
     { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
       .access = PL1_RW,
-      .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
+      .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el1),
       .resetvalue = 0 },
     REGINFO_SENTINEL
 };
@@ -1612,6 +1612,15 @@  static const ARMCPRegInfo aarch64_cp_reginfo[] = {
     { .name = "DCZID_EL0", .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_AA64,
       .resetvalue = 0x10 },
+    { .name = "TPIDR_EL0", .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
+      .access = PL0_RW, .type = ARM_CP_AA64,
+      .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
+    { .name = "TPIDRRO_EL0", .opc0 = 3, .opc1 = 3, .opc2 = 3,
+      .crn = 13, .crm = 0, .access = PL0_R|PL1_W, .type = ARM_CP_AA64,
+      .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
+    { .name = "TPIDR_EL1", .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
+      .access = PL1_RW, .type = ARM_CP_AA64,
+      .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
     REGINFO_SENTINEL
 };