From patchwork Thu Dec 12 07:57:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 300558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1DCFA2C007C for ; Thu, 12 Dec 2013 19:01:05 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752118Ab3LLH6V (ORCPT ); Thu, 12 Dec 2013 02:58:21 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15463 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751402Ab3LLH6S (ORCPT ); Thu, 12 Dec 2013 02:58:18 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 11 Dec 2013 23:58:16 -0800 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 12 Dec 2013 00:00:57 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 12 Dec 2013 00:00:57 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.327.1; Wed, 11 Dec 2013 23:58:17 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 11 Dec 2013 23:58:17 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rBC7vOpv017769; Wed, 11 Dec 2013 23:58:14 -0800 (PST) From: Hiroshi Doyu To: Stephen Warren , , , , , , , CC: Hiroshi Doyu , , , , , , , , Subject: [PATCHv7 04/12] driver/core: populate devices in order for IOMMUs Date: Thu, 12 Dec 2013 09:57:05 +0200 Message-ID: <1386835033-4701-5-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1386835033-4701-1-git-send-email-hdoyu@nvidia.com> References: <1386835033-4701-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org IOMMU devices on the bus need to be poplulated first, then iommu master devices are done later. With CONFIG_OF_IOMMU, "iommus=" DT binding would be used to identify whether a device can be an iommu msater or not. If a device can, we'll defer to populate that device till an iommu device is populated. Then, those deferred iommu master devices are populated and configured with help of the already populated iommu device. Signed-off-by: Hiroshi Doyu Cc: Greg Kroah-Hartman --- This is related to the following discussion: [RFC PATCH] Documentation: devicetree: add description for generic bus properties http://lists.infradead.org/pipermail/linux-arm-kernel/2013-November/215042.html v6: Spinned off only driver core part from: [PATCHv5 2/9] driver/core: populate devices in order for IOMMUs v5: Use "iommus=" binding instread of arm,smmu's "#stream-id-cells". v4: This is newly added, and the successor of the following RFC: [RFC][PATCHv3+ 1/2] driver/core: Add of_iommu_attach() http://lists.linuxfoundation.org/pipermail/iommu/2013-November/006914.html Signed-off-by: Hiroshi Doyu --- drivers/base/dd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/base/dd.c b/drivers/base/dd.c index 0605176..0605f52 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "base.h" #include "power/power.h" @@ -273,6 +274,10 @@ static int really_probe(struct device *dev, struct device_driver *drv) dev->driver = drv; + ret = of_iommu_attach(dev); + if (ret) + goto probe_failed; + /* If using pinctrl, bind pins now before probing */ ret = pinctrl_bind_pins(dev); if (ret)