From patchwork Thu Dec 12 07:57:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 300550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 800D92C00A1 for ; Thu, 12 Dec 2013 18:59:03 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752196Ab3LLH6n (ORCPT ); Thu, 12 Dec 2013 02:58:43 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1559 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751402Ab3LLH6l (ORCPT ); Thu, 12 Dec 2013 02:58:41 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 11 Dec 2013 23:58:40 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 12 Dec 2013 00:01:20 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 12 Dec 2013 00:01:20 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Wed, 11 Dec 2013 23:58:40 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 11 Dec 2013 23:58:40 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rBC7vOq3017769; Wed, 11 Dec 2013 23:58:37 -0800 (PST) From: Hiroshi Doyu To: Stephen Warren , , , , , , CC: Hiroshi Doyu , , , , , , , , Subject: [PATCHv7 10/12] iommu/tegra: smmu: allow duplicate ASID wirte Date: Thu, 12 Dec 2013 09:57:11 +0200 Message-ID: <1386835033-4701-11-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1386835033-4701-1-git-send-email-hdoyu@nvidia.com> References: <1386835033-4701-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The device, which belongs to the same ASID, can try to enable the same ASID as the other swgroup devices. This should be allowed but just skip the actual register write. If the write value is different, it will return -EINVAL. Signed-off-by: Hiroshi Doyu --- v4: This was the part of v3, which isn't used any more. [PATCHv3 10/19] iommu/tegra: smmu: Get "nvidia,swgroups" from DT Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index fd4479a..2b8a302 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -418,9 +418,13 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, offs = HWGRP_ASID_REG(i); val = smmu_read(smmu, offs); if (on) { - if (WARN_ON(val & mask)) - goto err_hw_busy; - val |= mask; + if (val) { + if (WARN_ON(val != mask)) + return -EINVAL; + goto skip; + } + + val = mask; memcpy(c->hwgrp, map, sizeof(u64)); } else { WARN_ON((val & mask) == mask); @@ -430,16 +434,8 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, } FLUSH_SMMU_REGS(smmu); +skip: return 0; - -err_hw_busy: - for_each_set_bit(i, map, TEGRA_SWGROUP_MAX) { - offs = HWGRP_ASID_REG(i); - val = smmu_read(smmu, offs); - val &= ~mask; - smmu_write(smmu, val, offs); - } - return -EBUSY; } static int smmu_client_set_hwgrp(struct smmu_client *c,