From patchwork Wed Dec 11 22:01:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 300445 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 762C42C00AC for ; Thu, 12 Dec 2013 09:04:15 +1100 (EST) Received: from localhost ([::1]:60467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vqrt6-0003wT-TF for incoming@patchwork.ozlabs.org; Wed, 11 Dec 2013 17:04:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54875) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vqrr7-0001Bb-36 for qemu-devel@nongnu.org; Wed, 11 Dec 2013 17:02:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vqrr5-0007OG-Ge for qemu-devel@nongnu.org; Wed, 11 Dec 2013 17:02:09 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43418) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vqrr5-0007NJ-9y for qemu-devel@nongnu.org; Wed, 11 Dec 2013 17:02:07 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Vqrqu-0001AS-6O; Wed, 11 Dec 2013 22:01:56 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 11 Dec 2013 22:01:55 +0000 Message-Id: <1386799315-4431-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386799315-4431-1-git-send-email-peter.maydell@linaro.org> References: <1386799315-4431-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Subject: [Qemu-devel] [PATCH v2 8/8] target-arm: A64: implement SVC, BRK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Graf Add decoding for the exception generating instructions, and implement SVC (syscalls) and BRK (software breakpoint). Signed-off-by: Alexander Graf Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 51 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 019a6ed..df4409b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -806,10 +806,57 @@ static void disas_system(DisasContext *s, uint32_t insn) } } -/* Exception generation */ +/* C3.2.3 Exception generation + * + * 31 24 23 21 20 5 4 2 1 0 + * +-----------------+-----+------------------------+-----+----+ + * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | + * +-----------------------+------------------------+----------+ + */ static void disas_exc(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int opc = extract32(insn, 21, 3); + int op2_ll = extract32(insn, 0, 5); + + switch (opc) { + case 0: + /* SVC, HVC, SMC; since we don't support the Virtualization + * or TrustZone extensions these all UNDEF except SVC. + */ + if (op2_ll != 1) { + unallocated_encoding(s); + break; + } + gen_exception_insn(s, 0, EXCP_SWI); + break; + case 1: + if (op2_ll != 0) { + unallocated_encoding(s); + break; + } + /* BRK */ + gen_exception_insn(s, 0, EXCP_BKPT); + break; + case 2: + if (op2_ll != 0) { + unallocated_encoding(s); + break; + } + /* HLT */ + unsupported_encoding(s, insn); + break; + case 5: + if (op2_ll < 1 || op2_ll > 3) { + unallocated_encoding(s); + break; + } + /* DCPS1, DCPS2, DCPS3 */ + unsupported_encoding(s, insn); + break; + default: + unallocated_encoding(s); + break; + } } /* C3.2.7 Unconditional branch (register)