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X-Received-From: 2607:f8b0:4002:c01::235 Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V2 PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch addes the Signed and Unsigned Divide Word Extended instructions which were introduced in Power ISA 2.06. V2: Eliminating extraneous code in the overflow case per comments from Richard Henderson. Fixed corner case bug in divweu (check for (RA) >= (RB)). Signed-off-by: Tom Musta --- target-ppc/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b274a15..3344fa9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -984,6 +984,72 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); /* divw divw. divwo divwo. */ GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); + +#define GEN_DIVWE(op, signed, compute_ov) \ +static void gen_##op(DisasContext *ctx) \ +{ \ + /* Need to use local temps because of the branches */ \ + TCGv ra = tcg_temp_local_new(); \ + TCGv rb = tcg_temp_local_new(); \ + int lbl_ov = gen_new_label(); \ + int lbl_rc = gen_new_label(); \ + \ + if (signed) { \ + TCGv tmp0; \ + /* divide by zero ? */ \ + tcg_gen_ext32s_i64(rb, cpu_gpr[rB(ctx->opcode)]); \ + tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \ + tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \ + /* check for MIN div -1 */ \ + int l3 = gen_new_label(); \ + tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \ + tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \ + gen_set_label(l3); \ + tcg_gen_div_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \ + tmp0 = tcg_temp_local_new(); \ + /* does the result fit in 32 bits? */ \ + tcg_gen_ext32s_i64(tmp0, cpu_gpr[rD(ctx->opcode)]); \ + tcg_gen_brcond_i64(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], tmp0, \ + lbl_ov); \ + tcg_temp_free(tmp0); \ + } else { /* unsigned */ \ + /* divide by zero ? */ \ + tcg_gen_ext32u_i64(rb, cpu_gpr[rB(ctx->opcode)]); \ + tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \ + /* is ra[32:63] >= rb[32:63] ? */ \ + tcg_gen_ext32u_i64(ra, cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_brcond_i64(TCG_COND_GEU, ra, rb, lbl_ov); \ + tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \ + tcg_gen_divu_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \ + } \ + \ + if (compute_ov) { \ + tcg_gen_movi_tl(cpu_ov, 0); \ + } \ + tcg_gen_br(lbl_rc); \ + \ + gen_set_label(lbl_ov); /* overflow handling */ \ + tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \ + \ + if (compute_ov) { \ + tcg_gen_movi_tl(cpu_ov, 1); \ + tcg_gen_movi_tl(cpu_so, 1); \ + } \ + \ + gen_set_label(lbl_rc); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ + } \ + \ + tcg_temp_free(ra); \ + tcg_temp_free(rb); \ +} + +GEN_DIVWE(divweu, 0, 0); +GEN_DIVWE(divweuo, 0, 1); +GEN_DIVWE(divwe, 1, 0); +GEN_DIVWE(divweo, 1, 1); + #if defined(TARGET_PPC64) static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, int sign, int compute_ov) @@ -9603,6 +9669,10 @@ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), +GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0x00000000, PPC_NONE, PPC2_ISA206), +GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206), +GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0x00000000, PPC_NONE, PPC2_ISA206), +GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0x00000000, PPC_NONE, PPC2_ISA206), #if defined(TARGET_PPC64) #undef GEN_INT_ARITH_DIVD