Patchwork [5/5] target-s390: Use little-endian ops for LOAD/STORE REVERSED

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Submitter Richard Henderson
Date Dec. 11, 2013, 7:30 p.m.
Message ID <1386790247-14267-6-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/300313/
State New
Headers show

Comments

Richard Henderson - Dec. 11, 2013, 7:30 p.m.
We don't need separate bswap with the new qemu_ld/st opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/insn-data.def | 12 +++++-----
 target-s390x/translate.c   | 58 ++++++++++++++++++++++++++++++----------------
 2 files changed, 44 insertions(+), 26 deletions(-)

Patch

diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index b42ebb6..dade9ba 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -423,9 +423,9 @@ 
 /* LOAD REVERSED */
     C(0xb91f, LRVR,    RRE,   Z,   0, r2_32u, new, r1_32, rev32, 0)
     C(0xb90f, LRVGR,   RRE,   Z,   0, r2_o, r1, 0, rev64, 0)
-    C(0xe31f, LRVH,    RXY_a, Z,   0, m2_16u, new, r1_16, rev16, 0)
-    C(0xe31e, LRV,     RXY_a, Z,   0, m2_32u, new, r1_32, rev32, 0)
-    C(0xe30f, LRVG,    RXY_a, Z,   0, m2_64, r1, 0, rev64, 0)
+    C(0xe31f, LRVH,    RXY_a, Z,   0, a2, new, r1_16, ld16r, 0)
+    C(0xe31e, LRV,     RXY_a, Z,   0, a2, new, r1_32, ld32r, 0)
+    C(0xe30f, LRVG,    RXY_a, Z,   0, a2, r1, 0, ld64r, 0)
 /* LOAD ZERO */
     C(0xb374, LZER,    RRE,   Z,   0, 0, 0, e1, zero, 0)
     C(0xb375, LZDR,    RRE,   Z,   0, 0, 0, f1, zero, 0)
@@ -635,9 +635,9 @@ 
     D(0xebf3, STOC,    RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
     D(0xebe3, STOCG,   RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
 /* STORE REVERSED */
-    C(0xe33f, STRVH,   RXY_a, Z,   la2, r1_16u, new, m1_16, rev16, 0)
-    C(0xe33e, STRV,    RXY_a, Z,   la2, r1_32u, new, m1_32, rev32, 0)
-    C(0xe32f, STRVG,   RXY_a, Z,   la2, r1_o, new, m1_64, rev64, 0)
+    C(0xe33f, STRVH,   RXY_a, Z,   r1_o, a2, 0, 0, st16r, 0)
+    C(0xe33e, STRV,    RXY_a, Z,   r1_o, a2, 0, 0, st32r, 0)
+    C(0xe32f, STRVG,   RXY_a, Z,   r1_o, a2, 0, 0, st64r, 0)
 
 /* STORE FPC */
     C(0xb29c, STFPC,   S,     Z,   0, a2, new, m2_32, efpc, 0)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index aa7d351..f1c000d 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2271,6 +2271,24 @@  static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_ld16r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_LEUW);
+    return NO_EXIT;
+}
+
+static ExitStatus op_ld32r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_LEUL);
+    return NO_EXIT;
+}
+
+static ExitStatus op_ld64r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_LEQ);
+    return NO_EXIT;
+}
+
 static ExitStatus op_loc(DisasContext *s, DisasOps *o)
 {
     DisasCompare c;
@@ -2855,12 +2873,6 @@  static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
-static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
-{
-    tcg_gen_bswap16_i64(o->out, o->in2);
-    return NO_EXIT;
-}
-
 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
 {
     tcg_gen_bswap32_i64(o->out, o->in2);
@@ -3313,6 +3325,24 @@  static ExitStatus op_st64(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_st16r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_LEUW);
+    return NO_EXIT;
+}
+
+static ExitStatus op_st32r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_LEUL);
+    return NO_EXIT;
+}
+
+static ExitStatus op_st64r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_LEQ);
+    return NO_EXIT;
+}
+
 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
 {
     TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
@@ -4089,12 +4119,14 @@  static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_in1_la1 0
 
+#ifndef CONFIG_USER_ONLY
 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
     o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
 }
 #define SPEC_in1_la2 0
+#endif
 
 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
@@ -4154,13 +4186,6 @@  static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_in2_r1_o 0
 
-static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
-{
-    o->in2 = tcg_temp_new_i64();
-    tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
-}
-#define SPEC_in2_r1_16u 0
-
 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     o->in2 = tcg_temp_new_i64();
@@ -4313,13 +4338,6 @@  static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_in2_m2_16s 0
 
-static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
-{
-    in2_a2(s, f, o);
-    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW);
-}
-#define SPEC_in2_m2_16u 0
-
 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);