diff mbox

[06/12] pcie: designware: Move register definition to the header file

Message ID 7bce26f60d847a136f748b5eeac15dc79a7d662e.1386752447.git.mohit.kumar@st.com
State Changes Requested
Headers show

Commit Message

Mohit KUMAR DCG Dec. 11, 2013, 9:38 a.m. UTC 
From: Pratyush Anand <pratyush.anand@st.com>

Move synopsis specific register definition from source file to header
file, so that they can be re-used by other files if needed.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 drivers/pci/host/pcie-designware.c |   42 ------------------------------------
 drivers/pci/host/pcie-designware.h |   42 ++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 42 deletions(-)

Comments

Jagan Teki Dec. 11, 2013, 11:38 a.m. UTC | #1 
On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> Move synopsis specific register definition from source file to header
> file, so that they can be re-used by other files if needed.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
>  drivers/pci/host/pcie-designware.h |   42 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 212b8b6..73aa13c 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -23,48 +23,6 @@
>
>  #include "pcie-designware.h"
>
> -/* Synopsis specific PCIE configuration registers */
> -#define PCIE_PORT_LINK_CONTROL         0x710
> -#define PORT_LINK_MODE_MASK            (0x3f << 16)
> -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> -
> -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> -
> -#define PCIE_MSI_ADDR_LO               0x820
> -#define PCIE_MSI_ADDR_HI               0x824
> -#define PCIE_MSI_INTR0_ENABLE          0x828
> -#define PCIE_MSI_INTR0_MASK            0x82C
> -#define PCIE_MSI_INTR0_STATUS          0x830
> -
> -#define PCIE_ATU_VIEWPORT              0x900
> -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> -#define PCIE_ATU_CR1                   0x904
> -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> -#define PCIE_ATU_CR2                   0x908
> -#define PCIE_ATU_ENABLE                        (0x1 << 31)
> -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> -#define PCIE_ATU_LOWER_BASE            0x90C
> -#define PCIE_ATU_UPPER_BASE            0x910
> -#define PCIE_ATU_LIMIT                 0x914
> -#define PCIE_ATU_LOWER_TARGET          0x918
> -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> -#define PCIE_ATU_UPPER_TARGET          0x91C
> -
>  static struct hw_pci dw_pci;
>
>  static unsigned long global_io_offset;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index c15379b..da1ed35 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
>  int dw_pcie_host_init(struct pcie_port *pp);
>
> +/* Synopsis specific PCIE configuration registers */
> +#define PCIE_PORT_LINK_CONTROL         0x710
> +#define PORT_LINK_MODE_MASK            (0x3f << 16)
> +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> +
> +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> +
> +#define PCIE_MSI_ADDR_LO               0x820
> +#define PCIE_MSI_ADDR_HI               0x824
> +#define PCIE_MSI_INTR0_ENABLE          0x828
> +#define PCIE_MSI_INTR0_MASK            0x82C
> +#define PCIE_MSI_INTR0_STATUS          0x830
> +
> +#define PCIE_ATU_VIEWPORT              0x900
> +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> +#define PCIE_ATU_CR1                   0x904
> +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> +#define PCIE_ATU_CR2                   0x908
> +#define PCIE_ATU_ENABLE                        (0x1 << 31)
> +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> +#define PCIE_ATU_LOWER_BASE            0x90C
> +#define PCIE_ATU_UPPER_BASE            0x910
> +#define PCIE_ATU_LIMIT                 0x914
> +#define PCIE_ATU_LOWER_TARGET          0x918
> +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> +#define PCIE_ATU_UPPER_TARGET          0x91C
> +
>  #endif /* _PCIE_DESIGNWARE_H */

Seems like none were using these headers except pcie-designware.c - if
ie the case
better to place it same place as before.
Mohit KUMAR DCG Dec. 11, 2013, 11:55 a.m. UTC | #2 
Hello Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]
> Sent: Wednesday, December 11, 2013 5:09 PM
> To: Mohit KUMAR DCG
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Pratyush ANAND; Jingoo Han; spear-devel
> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
> header file
> 
> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com>
> wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Move synopsis specific register definition from source file to header
> > file, so that they can be re-used by other files if needed.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-pci@vger.kernel.org
> > ---
> >  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
> >  drivers/pci/host/pcie-designware.h |   42
> ++++++++++++++++++++++++++++++++++++
> >  2 files changed, 42 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index 212b8b6..73aa13c 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -23,48 +23,6 @@
> >
> >  #include "pcie-designware.h"
> >
> > -/* Synopsis specific PCIE configuration registers */
> > -#define PCIE_PORT_LINK_CONTROL         0x710
> > -#define PORT_LINK_MODE_MASK            (0x3f << 16)
> > -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> > -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> > -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> > -
> > -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> > -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> > -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> > -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) -#define
> > PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) -#define
> > PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> > -
> > -#define PCIE_MSI_ADDR_LO               0x820
> > -#define PCIE_MSI_ADDR_HI               0x824
> > -#define PCIE_MSI_INTR0_ENABLE          0x828
> > -#define PCIE_MSI_INTR0_MASK            0x82C
> > -#define PCIE_MSI_INTR0_STATUS          0x830
> > -
> > -#define PCIE_ATU_VIEWPORT              0x900
> > -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> > -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> > -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> > -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> > -#define PCIE_ATU_CR1                   0x904
> > -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> > -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> > -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> > -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> > -#define PCIE_ATU_CR2                   0x908
> > -#define PCIE_ATU_ENABLE                        (0x1 << 31)
> > -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> > -#define PCIE_ATU_LOWER_BASE            0x90C
> > -#define PCIE_ATU_UPPER_BASE            0x910
> > -#define PCIE_ATU_LIMIT                 0x914
> > -#define PCIE_ATU_LOWER_TARGET          0x918
> > -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> > -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> > -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> > -#define PCIE_ATU_UPPER_TARGET          0x91C
> > -
> >  static struct hw_pci dw_pci;
> >
> >  static unsigned long global_io_offset; diff --git
> > a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h
> > index c15379b..da1ed35 100644
> > --- a/drivers/pci/host/pcie-designware.h
> > +++ b/drivers/pci/host/pcie-designware.h
> > @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);  void
> > dw_pcie_setup_rc(struct pcie_port *pp);  int dw_pcie_host_init(struct
> > pcie_port *pp);
> >
> > +/* Synopsis specific PCIE configuration registers */
> > +#define PCIE_PORT_LINK_CONTROL         0x710
> > +#define PORT_LINK_MODE_MASK            (0x3f << 16)
> > +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> > +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> > +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> > +
> > +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> > +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> > +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> > +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) #define
> > +PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) #define
> > +PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> > +
> > +#define PCIE_MSI_ADDR_LO               0x820
> > +#define PCIE_MSI_ADDR_HI               0x824
> > +#define PCIE_MSI_INTR0_ENABLE          0x828
> > +#define PCIE_MSI_INTR0_MASK            0x82C
> > +#define PCIE_MSI_INTR0_STATUS          0x830
> > +
> > +#define PCIE_ATU_VIEWPORT              0x900
> > +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> > +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> > +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> > +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> > +#define PCIE_ATU_CR1                   0x904
> > +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> > +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> > +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> > +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> > +#define PCIE_ATU_CR2                   0x908
> > +#define PCIE_ATU_ENABLE                        (0x1 << 31)
> > +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> > +#define PCIE_ATU_LOWER_BASE            0x90C
> > +#define PCIE_ATU_UPPER_BASE            0x910
> > +#define PCIE_ATU_LIMIT                 0x914
> > +#define PCIE_ATU_LOWER_TARGET          0x918
> > +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> > +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> > +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> > +#define PCIE_ATU_UPPER_TARGET          0x91C
> > +
> >  #endif /* _PCIE_DESIGNWARE_H */
> 
> Seems like none were using these headers except pcie-designware.c - if ie
> the case better to place it same place as before.

- We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, 
so move these to the separate header  file.

Thanks
Mohit
> 
> --
> Thanks,
> Jagan.
> --------
> Jagannadha Sutradharudu Teki,
> E: jagannadh.teki@gmail.com, P: +91-9676773388 Engineer - System
> Software Hacker U-boot - SPI Custodian and Zynq APSOC
> Ln: http://www.linkedin.com/in/jaganteki
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Jagan Teki Dec. 11, 2013, 12:04 p.m. UTC | #3 
On Wed, Dec 11, 2013 at 5:25 PM, Mohit KUMAR DCG <Mohit.KUMAR@st.com> wrote:
> Hello Jagan,
>
>> -----Original Message-----
>> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]
>> Sent: Wednesday, December 11, 2013 5:09 PM
>> To: Mohit KUMAR DCG
>> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> Pratyush ANAND; Jingoo Han; spear-devel
>> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
>> header file
>>
>> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com>
>> wrote:
>> > From: Pratyush Anand <pratyush.anand@st.com>
>> >
>> > Move synopsis specific register definition from source file to header
>> > file, so that they can be re-used by other files if needed.
>> >
>> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> > Cc: Mohit Kumar <mohit.kumar@st.com>
>> > Cc: Jingoo Han <jg1.han@samsung.com>
>> > Cc: spear-devel@list.st.com
>> > Cc: linux-pci@vger.kernel.org
>> > ---
>> >  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
>> >  drivers/pci/host/pcie-designware.h |   42
>> ++++++++++++++++++++++++++++++++++++
>> >  2 files changed, 42 insertions(+), 42 deletions(-)
>> >
>> > diff --git a/drivers/pci/host/pcie-designware.c
>> > b/drivers/pci/host/pcie-designware.c
>> > index 212b8b6..73aa13c 100644
>> > --- a/drivers/pci/host/pcie-designware.c
>> > +++ b/drivers/pci/host/pcie-designware.c
>> > @@ -23,48 +23,6 @@
>> >
>> >  #include "pcie-designware.h"
>> >
>> > -/* Synopsis specific PCIE configuration registers */
>> > -#define PCIE_PORT_LINK_CONTROL         0x710
>> > -#define PORT_LINK_MODE_MASK            (0x3f << 16)
>> > -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
>> > -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
>> > -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
>> > -
>> > -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
>> > -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
>> > -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
>> > -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) -#define
>> > PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) -#define
>> > PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
>> > -
>> > -#define PCIE_MSI_ADDR_LO               0x820
>> > -#define PCIE_MSI_ADDR_HI               0x824
>> > -#define PCIE_MSI_INTR0_ENABLE          0x828
>> > -#define PCIE_MSI_INTR0_MASK            0x82C
>> > -#define PCIE_MSI_INTR0_STATUS          0x830
>> > -
>> > -#define PCIE_ATU_VIEWPORT              0x900
>> > -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>> > -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
>> > -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>> > -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>> > -#define PCIE_ATU_CR1                   0x904
>> > -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
>> > -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
>> > -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
>> > -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
>> > -#define PCIE_ATU_CR2                   0x908
>> > -#define PCIE_ATU_ENABLE                        (0x1 << 31)
>> > -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
>> > -#define PCIE_ATU_LOWER_BASE            0x90C
>> > -#define PCIE_ATU_UPPER_BASE            0x910
>> > -#define PCIE_ATU_LIMIT                 0x914
>> > -#define PCIE_ATU_LOWER_TARGET          0x918
>> > -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
>> > -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
>> > -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
>> > -#define PCIE_ATU_UPPER_TARGET          0x91C
>> > -
>> >  static struct hw_pci dw_pci;
>> >
>> >  static unsigned long global_io_offset; diff --git
>> > a/drivers/pci/host/pcie-designware.h
>> > b/drivers/pci/host/pcie-designware.h
>> > index c15379b..da1ed35 100644
>> > --- a/drivers/pci/host/pcie-designware.h
>> > +++ b/drivers/pci/host/pcie-designware.h
>> > @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);  void
>> > dw_pcie_setup_rc(struct pcie_port *pp);  int dw_pcie_host_init(struct
>> > pcie_port *pp);
>> >
>> > +/* Synopsis specific PCIE configuration registers */
>> > +#define PCIE_PORT_LINK_CONTROL         0x710
>> > +#define PORT_LINK_MODE_MASK            (0x3f << 16)
>> > +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
>> > +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
>> > +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
>> > +
>> > +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
>> > +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
>> > +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
>> > +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) #define
>> > +PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) #define
>> > +PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
>> > +
>> > +#define PCIE_MSI_ADDR_LO               0x820
>> > +#define PCIE_MSI_ADDR_HI               0x824
>> > +#define PCIE_MSI_INTR0_ENABLE          0x828
>> > +#define PCIE_MSI_INTR0_MASK            0x82C
>> > +#define PCIE_MSI_INTR0_STATUS          0x830
>> > +
>> > +#define PCIE_ATU_VIEWPORT              0x900
>> > +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>> > +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
>> > +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>> > +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>> > +#define PCIE_ATU_CR1                   0x904
>> > +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
>> > +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
>> > +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
>> > +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
>> > +#define PCIE_ATU_CR2                   0x908
>> > +#define PCIE_ATU_ENABLE                        (0x1 << 31)
>> > +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
>> > +#define PCIE_ATU_LOWER_BASE            0x90C
>> > +#define PCIE_ATU_UPPER_BASE            0x910
>> > +#define PCIE_ATU_LIMIT                 0x914
>> > +#define PCIE_ATU_LOWER_TARGET          0x918
>> > +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
>> > +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
>> > +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
>> > +#define PCIE_ATU_UPPER_TARGET          0x91C
>> > +
>> >  #endif /* _PCIE_DESIGNWARE_H */
>>
>> Seems like none were using these headers except pcie-designware.c - if ie
>> the case better to place it same place as before.
>
> - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform,
> so move these to the separate header  file.
>

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Arnd Bergmann Dec. 11, 2013, 9:31 p.m. UTC | #4 
On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > 
> > Seems like none were using these headers except pcie-designware.c - if ie
> > the case better to place it same place as before.
> 
> - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, 
> so move these to the separate header  file.

I think it's better not to touch any of the registers from a platform-specific
driver. Better make a high-level function in the common code that the
spear driver can call to change this register.

	Arnd
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Jingoo Han Dec. 11, 2013, 10:48 p.m. UTC | #5 
On Thursday, December 12, 2013 6:32 AM, Arnd Bergmann wrote:
> On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > >
> > > Seems like none were using these headers except pcie-designware.c - if ie
> > > the case better to place it same place as before.
> >
> > - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform,
> > so move these to the separate header  file.
> 
> I think it's better not to touch any of the registers from a platform-specific
> driver. Better make a high-level function in the common code that the
> spear driver can call to change this register.

I also agree with Arnd's opinion.

Best regards,
Jingoo Han

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Mohit KUMAR DCG Dec. 12, 2013, 4:55 a.m. UTC | #6 
Hello Arnd,

> -----Original Message-----
> From: Jingoo Han [mailto:jg1.han@samsung.com]
> Sent: Thursday, December 12, 2013 4:19 AM
> To: Mohit KUMAR DCG; 'Arnd Bergmann'
> Cc: linux-arm-kernel@lists.infradead.org; 'Jagan Teki'; linux-
> pci@vger.kernel.org; spear-devel; Pratyush ANAND; 'Jingoo Han'
> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
> header file
> 
> On Thursday, December 12, 2013 6:32 AM, Arnd Bergmann wrote:
> > On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > > >
> > > > Seems like none were using these headers except pcie-designware.c
> > > > - if ie the case better to place it same place as before.
> > >
> > > - We have include these and used few like '
> > > PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, so move
> these to the separate header  file.
> >
> > I think it's better not to touch any of the registers from a
> > platform-specific driver. Better make a high-level function in the
> > common code that the spear driver can call to change this register.
> 
> I also agree with Arnd's opinion.

- As suggested, I will implement required functions in dw driver and hence no need to move register definitions.

Regards
Mohit 
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diff mbox

Patch

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 212b8b6..73aa13c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -23,48 +23,6 @@ 
 
 #include "pcie-designware.h"
 
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL		0x710
-#define PORT_LINK_MODE_MASK		(0x3f << 16)
-#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
-#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
-#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
-#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
-
-#define PCIE_MSI_ADDR_LO		0x820
-#define PCIE_MSI_ADDR_HI		0x824
-#define PCIE_MSI_INTR0_ENABLE		0x828
-#define PCIE_MSI_INTR0_MASK		0x82C
-#define PCIE_MSI_INTR0_STATUS		0x830
-
-#define PCIE_ATU_VIEWPORT		0x900
-#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
-#define PCIE_ATU_CR1			0x904
-#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
-#define PCIE_ATU_TYPE_IO		(0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
-#define PCIE_ATU_CR2			0x908
-#define PCIE_ATU_ENABLE			(0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
-#define PCIE_ATU_LOWER_BASE		0x90C
-#define PCIE_ATU_UPPER_BASE		0x910
-#define PCIE_ATU_LIMIT			0x914
-#define PCIE_ATU_LOWER_TARGET		0x918
-#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET		0x91C
-
 static struct hw_pci dw_pci;
 
 static unsigned long global_io_offset;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index c15379b..da1ed35 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -74,4 +74,46 @@  int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+/* Synopsis specific PCIE configuration registers */
+#define PCIE_PORT_LINK_CONTROL		0x710
+#define PORT_LINK_MODE_MASK		(0x3f << 16)
+#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
+#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
+#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
+#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
+
+#define PCIE_MSI_ADDR_LO		0x820
+#define PCIE_MSI_ADDR_HI		0x824
+#define PCIE_MSI_INTR0_ENABLE		0x828
+#define PCIE_MSI_INTR0_MASK		0x82C
+#define PCIE_MSI_INTR0_STATUS		0x830
+
+#define PCIE_ATU_VIEWPORT		0x900
+#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+#define PCIE_ATU_CR1			0x904
+#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+#define PCIE_ATU_TYPE_IO		(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_CR2			0x908
+#define PCIE_ATU_ENABLE			(0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE		0x90C
+#define PCIE_ATU_UPPER_BASE		0x910
+#define PCIE_ATU_LIMIT			0x914
+#define PCIE_ATU_LOWER_TARGET		0x918
+#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET		0x91C
+
 #endif /* _PCIE_DESIGNWARE_H */