From patchwork Fri Dec 6 17:36:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 298142 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5F8582C00A8 for ; Sat, 7 Dec 2013 04:37:27 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=xZ6OqRofy1mOMWtqGm0y6Vcg1EIcGxxunBjvX+pyEVdNRX zJEkED0UAiCk4KjieSzhaoAqp2QpcccCHI7Cxodoe03HnAtPPMyTxsEBdsZ6soPl cqaypWRaXyuG77ilw3Vn4QHni/Wpq9K41o3Xaf3r2Qw5N6Gl4kzYp2jfbdDOE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=CPNu+y4g/LBYybmUNLVbhW3gErU=; b=BvQseFqb2E2/eM+RVYGp oiROUEsI3D6TaSujcYQIIDqqOx6ME/MjZZ/Y4VgESnTViGPA273iYHmrJIfucAhV 1imBZ6O29ZG8CThi5ITGvfV9CpdTQLbwHOryPg4CPtI00TP9oGtTWsOqVSfJy4zE dYgzMN6Ovx7NQ+ZW4AFli4A= Received: (qmail 3788 invoked by alias); 6 Dec 2013 17:36:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3752 invoked by uid 89); 6 Dec 2013 17:36:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from Unknown (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Dec 2013 17:36:41 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 06 Dec 2013 17:36:32 +0000 Received: from [10.1.203.80] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Dec 2013 17:36:30 +0000 Message-ID: <52A20B1D.8010901@arm.com> Date: Fri, 06 Dec 2013 17:36:29 +0000 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch, AArch64] [6/6] Implement support for Crypto -- PMULL.64. X-MC-Unique: 113120617363217201 X-IsSubscribed: yes Hi, This patch implements support for crypto pmull.64. Tested on aarch64-none-elf. OK for trunk? Thanks, Tejas. 2013-12-06 Tejas Belagod gcc/ * config/aarch64/aarch64-builtins.c: Define builtin types for poly64_t poly128_t. * aarch64/aarch64-simd-builtins.def: Update builtins table. * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi, aarch64_crypto_pmullv2di): New. * config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for poly64x2_t mangler. * config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define. (vmull_p64, vmull_high_p64): New. * config/aarch64/iterators.md (UNSPEC_PMULL<2>): New. testsuite/ * gcc.target/aarch64/pmull.c: New. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index f4d23e7..748206f 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -487,6 +487,10 @@ aarch64_init_simd_builtins (void) make_signed_type (GET_MODE_PRECISION (QImode)); tree aarch64_simd_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); + tree aarch64_simd_polyDI_type_node = + make_unsigned_type (GET_MODE_PRECISION (DImode)); + tree aarch64_simd_polyTI_type_node = + make_unsigned_type (GET_MODE_PRECISION (TImode)); /* Scalar type nodes. */ tree aarch64_simd_intQI_type_node = aarch64_build_type (QImode, false); @@ -526,6 +530,10 @@ aarch64_init_simd_builtins (void) "__builtin_aarch64_simd_poly8"); (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyHI_type_node, "__builtin_aarch64_simd_poly16"); + (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyDI_type_node, + "__builtin_aarch64_simd_poly64"); + (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyTI_type_node, + "__builtin_aarch64_simd_poly128"); (*lang_hooks.types.register_builtin_type) (aarch64_simd_intTI_type_node, "__builtin_aarch64_simd_ti"); (*lang_hooks.types.register_builtin_type) (aarch64_simd_intEI_type_node, diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index dd21d9c..ec010f3 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -381,3 +381,7 @@ VAR1 (TERNOP, crypto_sha256h2, 0, v4si) VAR1 (BINOP, crypto_sha256su0, 0, v4si) VAR1 (TERNOP, crypto_sha256su1, 0, v4si) + + /* Implemented by aarch64_crypto_pmull. */ + VAR1 (BINOP, crypto_pmull, 0, di) + VAR1 (BINOP, crypto_pmull, 0, v2di) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5bcada2..6d3d70e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4173,3 +4173,25 @@ "sha256su1\\t%0.4s, %2.4s, %3.4s" [(set_attr "type" "crypto_sha256_slow")] ) + +;; pmull + +(define_insn "aarch64_crypto_pmulldi" + [(set (match_operand:TI 0 "register_operand" "=w") + (unspec:TI [(match_operand:DI 1 "register_operand" "w") + (match_operand:DI 2 "register_operand" "w")] + UNSPEC_PMULL))] + "TARGET_SIMD && TARGET_CRYPTO" + "pmull\\t%0.1q, %1.1d, %2.1d" + [(set_attr "type" "neon_mul_d_long")] +) + +(define_insn "aarch64_crypto_pmullv2di" + [(set (match_operand:TI 0 "register_operand" "=w") + (unspec:TI [(match_operand:V2DI 1 "register_operand" "w") + (match_operand:V2DI 2 "register_operand" "w")] + UNSPEC_PMULL2))] + "TARGET_SIMD && TARGET_CRYPTO" + "pmull2\\t%0.1q, %1.2d, %2.2d" + [(set_attr "type" "neon_mul_d_long")] +) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c85947a..963bd2e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6370,6 +6370,7 @@ static aarch64_simd_mangle_map_entry aarch64_simd_mangle_map[] = { { V2DFmode, "__builtin_aarch64_simd_df", "13__Float64x2_t" }, { V16QImode, "__builtin_aarch64_simd_poly8", "12__Poly8x16_t" }, { V8HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x8_t" }, + { V2DImode, "__builtin_aarch64_simd_poly64", "12__Poly64x2_t" }, { VOIDmode, NULL, NULL } }; diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index d038e37..509b1a7 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -75,6 +75,8 @@ typedef __builtin_aarch64_simd_poly8 poly8x16_t __attribute__ ((__vector_size__ (16))); typedef __builtin_aarch64_simd_poly16 poly16x8_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_aarch64_simd_poly64 poly64x2_t + __attribute__ ((__vector_size__ (16))); typedef __builtin_aarch64_simd_uqi uint8x16_t __attribute__ ((__vector_size__ (16))); typedef __builtin_aarch64_simd_uhi uint16x8_t @@ -88,6 +90,8 @@ typedef float float32_t; typedef double float64_t; typedef __builtin_aarch64_simd_poly8 poly8_t; typedef __builtin_aarch64_simd_poly16 poly16_t; +typedef __builtin_aarch64_simd_poly64 poly64_t; +typedef __builtin_aarch64_simd_poly128 poly128_t; typedef struct int8x8x2_t { @@ -23254,6 +23258,20 @@ vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15) ((int32x4_t) tw0_3, (int32x4_t) w8_11, (int32x4_t) w12_15); } +static __inline poly128_t +vmull_p64 (poly64_t a, poly64_t b) +{ + return + (poly128_t) __builtin_aarch64_crypto_pmulldi ((int64x1_t)a, (int64x1_t)b); +} + +static __inline poly128_t +vmull_high_p64 (poly64x2_t a, poly64x2_t b) +{ + return + (poly128_t) __builtin_aarch64_crypto_pmullv2di ((int64x2_t)a, (int64x2_t)b); +} + #endif /* vshl */ diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index ae94e5a..2f4864c 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -277,6 +277,8 @@ UNSPEC_SHA256H2 ; Used in aarch64-simd.md. UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. + UNSPEC_PMULL ; Used in aarch64-simd.md. + UNSPEC_PMULL2 ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/aarch64/pmull.c b/gcc/testsuite/gcc.target/aarch64/pmull.c new file mode 100644 index 0000000..55079c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pmull.c @@ -0,0 +1,23 @@ + +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+crypto" } */ + +#include "arm_neon.h" + +poly128_t +test_vmull_p64 (poly64_t a, poly64_t b) +{ + return vmull_p64 (a, b); +} + +/* { dg-final { scan-assembler "pmull\\tv" } } */ + +poly128_t +test_vmull_high_p64 (poly64x2_t a, poly64x2_t b) +{ + return vmull_high_p64 (a, b); +} + +/* { dg-final { scan-assembler "pmull2\\tv" } } */ + +/* { dg-final { cleanup-saved-temps } } */