From patchwork Thu Dec 5 18:22:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 297348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 61C2C2C007B for ; Fri, 6 Dec 2013 05:23:29 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; q=dns; s=default; b=cJ8S/xbIYXSPKSK2tXq9l5XNu/rOK Bj2OHD0Ac3EzeJjEjrqVx3xxJXHKLXUIOdB3u1XrxpJuM570pFr2usWFKfHG0eGI 2DZ/qyfybcr9aNzzcX25rF9TQLYP3WiILtJWZUqgTd7RKTgxSzfoehAu1Jh5hbtO NTdlOXppUzUAgw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; s=default; bh=PHZ14zWck64wC08Sg6xhf+C7TYU=; b=HdB 9gTaAt9E4KHFo2Czp23jZHALjpIgj6g/tw1QqztnClGwvaELkzGmDXs5BP9y/aU5 NJjGH1fWfVjbqB2u1afuEibJrCc9hNuQJXQuyrcEtzgQrWms4LCcyLyORMD2RLLi cxucsHPCz+fCztwYYpHrF/2WOsWW2M64MmpnHtSE= Received: (qmail 4714 invoked by alias); 5 Dec 2013 18:23:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4704 invoked by uid 89); 5 Dec 2013 18:23:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_05, NO_DNS_FOR_FROM autolearn=no version=3.3.2 X-HELO: mga11.intel.com Received: from Unknown (HELO mga11.intel.com) (192.55.52.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 05 Dec 2013 18:23:19 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 05 Dec 2013 10:23:05 -0800 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by fmsmga002.fm.intel.com with ESMTP; 05 Dec 2013 10:22:59 -0800 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id 2D39580BDD; Thu, 5 Dec 2013 10:22:55 -0800 (PST) Date: Thu, 5 Dec 2013 10:22:54 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH] Add -mtune=ia support Message-ID: <20131205182254.GA17941@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Hi, We'd like to add a new -mtune=ia option for x86 to optimize for both Haswell and Silvermont. Currently, -mtune=ia is aliased to -mtune=slm. We will improve it further for Haswell and Silvermont. Later, we will update it to future Intel processors. OK for trunk? Thanks. H.J. --- 2013-12-05 H.J. Lu * config.gcc: Support --with-cpu=ia. * config/i386/i386.c (cpu_names): Add "ia". (processor_alias_table): Likewise. (ix86_option_override_internal): Disallow -march=ia. * config/i386/i386.h (target_cpu_default): Add TARGET_CPU_DEFAULT_ia. * doc/invoke.texi: Document -mtune=ia. diff --git a/gcc/config.gcc b/gcc/config.gcc index 1f20f18..dd180a0 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1398,7 +1398,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'` need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1407,7 +1407,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic ia atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1519,7 +1519,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*) tmake_file="$tmake_file i386/t-sol2-64" need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1528,7 +1528,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic ia atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1604,7 +1604,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) if test x$enable_targets = xall; then tm_defines="${tm_defines} TARGET_BI_ARCH=1" case X"${with_cpu}" in - Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1613,7 +1613,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic ia atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -3664,7 +3664,7 @@ case "${target}" in esac # OK ;; - "" | x86-64 | generic | native \ + "" | x86-64 | generic | ia | native \ | k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \ | opteron-sse3 | athlon-fx | bdver4 | bdver3 | bdver2 \ | bdver1 | btver2 | btver1 | amdfam10 | barcelona \ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 0f6612d..382f8fb 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2434,6 +2434,7 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = "core-avx2", "atom", "slm", + "ia", "geode", "k6", "k6-2", @@ -3142,6 +3143,9 @@ ix86_option_override_internal (bool main_args_p, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR}, + {"ia", PROCESSOR_SLM, CPU_SLM, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 + | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR}, {"geode", PROCESSOR_GEODE, CPU_GEODE, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW}, {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX}, @@ -3628,6 +3632,9 @@ ix86_option_override_internal (bool main_args_p, if (!strcmp (opts->x_ix86_arch_string, "generic")) error ("generic CPU can be used only for %stune=%s %s", prefix, suffix, sw); + else if (!strcmp (ix86_arch_string, "ia")) + error ("ia CPU can be used only for %stune=%s %s", + prefix, suffix, sw); else if (!strncmp (opts->x_ix86_arch_string, "generic", 7) || i == pta_size) error ("bad value (%s) for %sarch=%s %s", opts->x_ix86_arch_string, prefix, suffix, sw); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 113c75e..db81aea 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -626,6 +626,7 @@ enum target_cpu_default TARGET_CPU_DEFAULT_haswell, TARGET_CPU_DEFAULT_atom, TARGET_CPU_DEFAULT_slm, + TARGET_CPU_DEFAULT_ia, TARGET_CPU_DEFAULT_geode, TARGET_CPU_DEFAULT_k6, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 704d474..ed5b60f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14743,7 +14743,7 @@ then @option{-mtune=pentium4} generates code that is tuned for Pentium 4 but still runs on i686 machines. The choices for @var{cpu-type} are the same as for @option{-march}. -In addition, @option{-mtune} supports an extra choice for @var{cpu-type}: +In addition, @option{-mtune} supports 2 extra choices for @var{cpu-type}: @table @samp @item generic @@ -14764,6 +14764,26 @@ indicates the instruction set the compiler can use, and there is no generic instruction set applicable to all processors. In contrast, @option{-mtune} indicates the processor (or, in this case, collection of processors) for which the code is optimized. + +@item ia +Produce code optimized for the most current Intel processors, which are +Haswell and Silvermont for this version of GCC. If you know the CPU +on which your code will run, then you should use the corresponding +@option{-mtune} or @option{-march} option instead of @option{-mtune=ia}. +But, if you want your application performs better on both Haswell and +Silvermont, then you should use this option. + +As new Intel processors are deployed in the marketplace, the behavior of +this option will change. Therefore, if you upgrade to a newer version of +GCC, code generation controlled by this option will change to reflect +the most current Intel processors at the time that version of GCC is +released. + +There is no @option{-march=ia} option because @option{-march} indicates +the instruction set the compiler can use, and there is no common +instruction set applicable to all processors. In contrast, +@option{-mtune} indicates the processor (or, in this case, collection of +processors) for which the code is optimized. @end table @item -mcpu=@var{cpu-type}