====================================================================
b/board/samsung/tiny4412/Makefile
new file mode 100644
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights
reserved.
+# Sanghee Kim <sh0130.kim@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tiny4412.o
b/board/samsung/tiny4412/tiny4412.c
new file mode 100644
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct exynos4x12_gpio_part1 *gpio1;
+static struct exynos4x12_gpio_part2 *gpio2;
+
+static unsigned int board_rev = -1;
+
+static inline u32 get_model_rev(void);
+
+static void check_hw_revision(void)
+{
+ int modelrev = 0;
+ int i;
+
+ gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+
+ /*
+ * GPM1[1:0]: MODEL_REV[1:0]
+ * Don't set as pull-none for these N/C pin.
+ * TRM say that it may cause unexcepted state and leakage current.
+ * and pull-none is only for output function.
+ */
+ for (i = 0; i < 2; i++)
+ s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
+
+ /* GPM1[5:2]: HW_REV[3:0] */
+ for (i = 2; i < 6; i++) {
+ s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
+ s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE);
+ }
+
+ /* GPM1[1:0]: MODEL_REV[1:0] */
+ for (i = 0; i < 2; i++)
+ modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i);
+
+ /* board_rev[15:8] = model */
+ board_rev = modelrev << 8;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board:\tTINY4412\n");
+ return 0;
+}
+#endif
+
+static void show_hw_revision(void)
+{
+ printf("HW Revision:\t0x%04x\n", board_rev);
+}
+
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+
+static inline u32 get_model_rev(void)
+{
+ return (board_rev >> 8) & 0xff;
+}
+
+static void board_external_gpio_init(void)
+{
+ gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+
+ /*
+ * some pins which in alive block are connected with external pull-up
+ * but it's default setting is pull-down.
+ * if that pin set as input then that floated
+ */
+
+ s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
+ s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */
+ s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */
+}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+static void board_init_i2c(void)
+{
+ gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+
+ /* I2C_7 */
+ s5p_gpio_direction_output(&gpio1->d0, 2, 1);
+ s5p_gpio_direction_output(&gpio1->d0, 3, 1);
+
+ /* I2C_8 */
+ s5p_gpio_direction_output(&gpio1->f1, 4, 1);
+ s5p_gpio_direction_output(&gpio1->f1, 5, 1);
+
+ /* I2C_9 */
+ s5p_gpio_direction_output(&gpio2->m2, 1, 1);
+ s5p_gpio_direction_output(&gpio2->m2, 0, 1);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+ s5p_gpio_cfg_pin(&gpio2->m4, 1, GPIO_INPUT);
+ s5p_gpio_set_pull(&gpio2->m4, 1, GPIO_PULL_NONE);
+
+ check_hw_revision();
+ board_external_gpio_init();
+
+ gd->flags |= GD_FLG_DISABLE_CONSOLE;
+
+ return 0;
+}
+
+
+int board_init(void)
+{
+
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 size_mb;
+
+ size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
+
+ gd->ram_size = size_mb << 20;
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int err0, err2 = 0;
+
+ gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+
+ /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
+ s5p_gpio_direction_output(&gpio2->k0, 2, 1);
+ s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
+
+ /*
+ * eMMC GPIO:
+ * SDR 8-bit@48MHz at MMC0
+ * GPK0[0] SD_0_CLK(2)
+ * GPK0[1] SD_0_CMD(2)
+ * GPK0[2] SD_0_CDn -> Not used
+ * GPK0[3:6] SD_0_DATA[0:3](2)
+ * GPK1[3:6] SD_0_DATA[0:3](3)
+ *
+ * DDR 4-bit@26MHz at MMC4
+ * GPK0[0] SD_4_CLK(3)
+ * GPK0[1] SD_4_CMD(3)
+ * GPK0[2] SD_4_CDn -> Not used
+ * GPK0[3:6] SD_4_DATA[0:3](3)
+ * GPK1[3:6] SD_4_DATA[4:7](4)
+ */
+
+ err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+
+ /*
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
+ */
+ if (err0)
+ debug("SDMMC0 not configured\n");
+ else
+ err0 = s5p_mmc_init(0, 8);
+
+ /* T-flash detect */
+ s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
+ s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+
+ /*
+ * Check the T-flash detect pin
+ * GPX3[4] T-flash detect pin
+ */
+ if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
+ err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err2)
+ debug("SDMMC2 not configured\n");
+ else
+ err2 = s5p_mmc_init(2, 4);
+ }
+
+ return err0 & err2;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ setenv("model", "GT-I8800");
+ setenv("board", "TINY4412");
+
+ show_hw_revision();
+
+ return 0;
+}
+#endif
@@ -276,6 +276,7 @@ Active arm armv7 exynos
samsung smdk5250
Active arm armv7 exynos samsung smdkv310
smdkv310 -
Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung trats
trats -
Lukasz Majewski <l.majewski@samsung.com>
Active arm armv7 exynos samsung trats2
trats2 -
Piotr Wilczek <p.wilczek@samsung.com>
+Active arm armv7 exynos samsung tiny4412
tiny4412 -
Tomoya Getsufuki
<ayaka@mail.soulik.info>
Active arm armv7 exynos samsung
universal_c210 s5pc210_universal -
Minkyu Kang
<mk7.kang@samsung.com>
Active arm armv7 highbank - highbank
highbank -
Rob Herring <rob.herring@calxeda.com>
Active arm armv7 mx5 denx m53evk
m53evk
m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg
Marek Vasut
<marek.vasut@gmail.com>
new file mode 100644
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* which is in a S5P Family */
+#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
+
+#define PLATFORM_NO_UNALIGNED
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x10502000
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
+#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
+#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
+#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
+#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
+#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
+#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
+#define PHYS_SDRAM_END 0x80000000
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_TEXT_BASE 0x78100000
+
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+
+/* MACH_TYPE_TINY4412 */
+#define MACH_TYPE_TINY4412 4608
+#define CONFIG_MACH_TYPE MACH_TYPE_TINY4412
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL0
+
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_BAUDRATE 115200
+
+/* It should define before config_cmd_default.h */
+#define CONFIG_SYS_NO_FLASH
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_GPT
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_CMD_EXT2
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
+#undef CONFIG_CMD_NET
+
+/* MMC */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV 2
+
+/* PWM */
+#define CONFIG_PWM
+
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC0,115200n8\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Tizen - partitions definitions */
+#define PARTS_CSA "csa-mmc"
+#define PARTS_BOOTLOADER "u-boot"
+#define PARTS_BOOT "boot"
+#define PARTS_ROOT "platform"
+#define PARTS_DATA "data"
+#define PARTS_CSC "csc"
+#define PARTS_UMS "ums"
+
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+ "name="PARTS_BOOTLOADER",size=60MiB," \
+ "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
+ "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+ "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootk=" \
+ "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+ "updatemmc=" \
+ "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
+ "mmc boot 0 1 1 0\0" \
+ "updatebackup=" \
+ "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
+ " mmc boot 0 1 1 0\0" \
+ "updatebootb=" \
+ "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
+ "updateuboot=" \
+ "mmc write 0x50000000 0x80 0x400\0" \
+ "mmcboot=" \
+ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+ "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+ "boottrace=setenv opts initcall_debug; run bootcmd\0" \
+ "verify=n\0" \
+ "rootfstype=ext4\0" \
+ "console=" CONFIG_DEFAULT_CONSOLE \
+ "kernelname=uImage\0" \
+ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+ "0x40007FC0 ${kernelname}\0" \
+ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
+ "${fdtfile}\0" \
+ "mmcdev=0\0" \
+ "mmcbootpart=2\0" \
+ "mmcrootpart=5\0" \
+ "opts=always_resume=1\0" \
+ "partitions=" PARTS_DEFAULT \
+ "uartpath=ap\0" \
+ "usbpath=ap\0" \
+ "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
+ "consoleoff=set console console=ram; save; reset\0" \
+ "spladdr=0x40000100\0" \
+ "splsize=0x200\0" \
+ "splfile=falcon.bin\0" \
+ "spl_export=" \
+ "setexpr spl_imgsize ${splsize} + 8 ;" \
+ "setenv spl_imgsize 0x${spl_imgsize};" \
+ "setexpr spl_imgaddr ${spladdr} - 8 ;" \
+ "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
+ "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
+ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
+ "spl export atags 0x40007FC0;" \
+ "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
+ "mw.l ${spl_addr_tmp} ${splsize};" \
+ "ext4write mmc ${mmcdev}:${mmcbootpart}" \
+ " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
+ "setenv spl_imgsize;" \
+ "setenv spl_imgaddr;" \
+ "setenv spl_addr_tmp;\0" \
+ "fdtaddr=40800000\0" \
+ "fdtfile=exynos4412-trats2.dtb\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "Tiny4412 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+
+#endif /* __CONFIG_H */