Patchwork [2/2] target-i386: Intel MPX

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Submitter Liu, Jinsong
Date Dec. 2, 2013, 4:42 p.m.
Message ID <DE8DF0795D48FD4CA783C40EC8292335013F60B1@SHSMSX101.ccr.corp.intel.com>
Download mbox | patch
Permalink /patch/295959/
State New
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Comments

Liu, Jinsong - Dec. 2, 2013, 4:42 p.m.
From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Tue, 3 Dec 2013 05:08:19 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX

Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4.

Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
 target-i386/cpu.c |    4 ++++
 target-i386/cpu.h |   10 +++++++---
 2 files changed, 11 insertions(+), 3 deletions(-)
Paolo Bonzini - Dec. 2, 2013, 5:32 p.m.
Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
> From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <jinsong.liu@intel.com>
> Date: Tue, 3 Dec 2013 05:08:19 +0800
> Subject: [PATCH 2/2] target-i386: Intel MPX
> 
> Add some MPX related definiation, and hardcode sizes and offsets
> of xsave features 3 and 4.
> 
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>

kvm_get/put_xsave support is still missing.

> ---
>  target-i386/cpu.c |    4 ++++
>  target-i386/cpu.h |   10 +++++++---
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 544b57f..52ca029 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
>  static const ExtSaveArea ext_save_areas[] = {
>      [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
>              .offset = 0x240, .size = 0x100 },
> +    [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> +            .offset = 0x3c0, .size = 0x40  },
> +    [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> +            .offset = 0x400, .size = 0x10  },
>  };
>  
>  const char *get_register_name_32(unsigned int reg)
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index ea373e8..2975644 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -380,9 +380,12 @@
>  
>  #define MSR_VM_HSAVE_PA                 0xc0010117
>  
> -#define XSTATE_FP                       1
> -#define XSTATE_SSE                      2
> -#define XSTATE_YMM                      4
> +#define XSTATE_FP                       (1ULL << 0)
> +#define XSTATE_SSE                      (1ULL << 1)
> +#define XSTATE_YMM                      (1ULL << 2)
> +#define XSTATE_BNDREGS                  (1ULL << 3)
> +#define XSTATE_BNDCSR                   (1ULL << 4)
> +
>  
>  /* CPUID feature words */
>  typedef enum FeatureWord {
> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_EBX_ERMS     (1 << 9)
>  #define CPUID_7_0_EBX_INVPCID  (1 << 10)
>  #define CPUID_7_0_EBX_RTM      (1 << 11)
> +#define CPUID_7_0_EBX_MPX      (1 << 14)
>  #define CPUID_7_0_EBX_RDSEED   (1 << 18)
>  #define CPUID_7_0_EBX_ADX      (1 << 19)
>  #define CPUID_7_0_EBX_SMAP     (1 << 20)
>
Liu, Jinsong - Dec. 4, 2013, 7:39 a.m.
Paolo Bonzini wrote:
> Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
>> From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00
>> 2001 From: Liu Jinsong <jinsong.liu@intel.com>
>> Date: Tue, 3 Dec 2013 05:08:19 +0800
>> Subject: [PATCH 2/2] target-i386: Intel MPX
>> 
>> Add some MPX related definiation, and hardcode sizes and offsets
>> of xsave features 3 and 4.
>> 
>> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> 
> kvm_get/put_xsave support is still missing.

Thanks! Will add kvm_get/put_xsave support and send out later.

Jinsong

> 
>> ---
>>  target-i386/cpu.c |    4 ++++
>>  target-i386/cpu.h |   10 +++++++---
>>  2 files changed, 11 insertions(+), 3 deletions(-)
>> 
>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>> index 544b57f..52ca029 100644
>> --- a/target-i386/cpu.c
>> +++ b/target-i386/cpu.c
>> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
>>  static const ExtSaveArea ext_save_areas[] = {
>>      [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
>>              .offset = 0x240, .size = 0x100 },
>> +    [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
>> +            .offset = 0x3c0, .size = 0x40  },
>> +    [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
>> +            .offset = 0x400, .size = 0x10  },
>>  };
>> 
>>  const char *get_register_name_32(unsigned int reg)
>> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
>> index ea373e8..2975644 100644
>> --- a/target-i386/cpu.h
>> +++ b/target-i386/cpu.h
>> @@ -380,9 +380,12 @@
>> 
>>  #define MSR_VM_HSAVE_PA                 0xc0010117
>> 
>> -#define XSTATE_FP                       1
>> -#define XSTATE_SSE                      2
>> -#define XSTATE_YMM                      4
>> +#define XSTATE_FP                       (1ULL << 0)
>> +#define XSTATE_SSE                      (1ULL << 1)
>> +#define XSTATE_YMM                      (1ULL << 2)
>> +#define XSTATE_BNDREGS                  (1ULL << 3)
>> +#define XSTATE_BNDCSR                   (1ULL << 4) +
>> 
>>  /* CPUID feature words */
>>  typedef enum FeatureWord {
>> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>>  #define CPUID_7_0_EBX_ERMS     (1 << 9)
>>  #define CPUID_7_0_EBX_INVPCID  (1 << 10)
>>  #define CPUID_7_0_EBX_RTM      (1 << 11)
>> +#define CPUID_7_0_EBX_MPX      (1 << 14)
>>  #define CPUID_7_0_EBX_RDSEED   (1 << 18)
>>  #define CPUID_7_0_EBX_ADX      (1 << 19)
>>  #define CPUID_7_0_EBX_SMAP     (1 << 20)

Patch

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..52ca029 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -336,6 +336,10 @@  typedef struct ExtSaveArea {
 static const ExtSaveArea ext_save_areas[] = {
     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
             .offset = 0x240, .size = 0x100 },
+    [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+            .offset = 0x3c0, .size = 0x40  },
+    [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+            .offset = 0x400, .size = 0x10  },
 };
 
 const char *get_register_name_32(unsigned int reg)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ea373e8..2975644 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,12 @@ 
 
 #define MSR_VM_HSAVE_PA                 0xc0010117
 
-#define XSTATE_FP                       1
-#define XSTATE_SSE                      2
-#define XSTATE_YMM                      4
+#define XSTATE_FP                       (1ULL << 0)
+#define XSTATE_SSE                      (1ULL << 1)
+#define XSTATE_YMM                      (1ULL << 2)
+#define XSTATE_BNDREGS                  (1ULL << 3)
+#define XSTATE_BNDCSR                   (1ULL << 4)
+
 
 /* CPUID feature words */
 typedef enum FeatureWord {
@@ -545,6 +548,7 @@  typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_EBX_ERMS     (1 << 9)
 #define CPUID_7_0_EBX_INVPCID  (1 << 10)
 #define CPUID_7_0_EBX_RTM      (1 << 11)
+#define CPUID_7_0_EBX_MPX      (1 << 14)
 #define CPUID_7_0_EBX_RDSEED   (1 << 18)
 #define CPUID_7_0_EBX_ADX      (1 << 19)
 #define CPUID_7_0_EBX_SMAP     (1 << 20)