From patchwork Fri Nov 29 12:19:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 295414 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B96AA2C00CB for ; Sat, 30 Nov 2013 01:13:01 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VmN7o-00042w-Je; Fri, 29 Nov 2013 12:24:48 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VmN7m-0007NN-Ie; Fri, 29 Nov 2013 12:24:46 +0000 Received: from bombadil.infradead.org ([2001:1868:205::9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VmN3m-0006tu-0s for linux-mtd@merlin.infradead.org; Fri, 29 Nov 2013 12:20:38 +0000 Received: from mail-yh0-f51.google.com ([209.85.213.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VmN3k-00037z-S1 for linux-mtd@lists.infradead.org; Fri, 29 Nov 2013 12:20:37 +0000 Received: by mail-yh0-f51.google.com with SMTP id c41so5102216yho.24 for ; Fri, 29 Nov 2013 04:20:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=toAGQ5hvKV1gbyfHw/ayrKtO+OpnzJp+OqXQNs8on7Q=; b=kwkoA6i5t3JtrAGBDJvkAA1AM6dVAGe/6Cwi6NUTB5DRktuRmJBIVvigxKRa4tobuF uoVCZvNosrypvTnpLKMMH7Ej/Qb4unPhaaWSFmO2xZTi4KYcWnWFHPNR/91hlls0CfW/ FEpkFg/14KcSoSSC2uxbB5tfsV1vx59Xi4j/dIUWlI7idrACsH4QSu5+iv1b+RJ3+YND yVHiTp+OdGcGAEFf5ZBSRdEbk3AO+Af3gZhewuf0NT06/LmWqT+0JpydLbyGSflZyUy8 NdTV8Jiw66qd+hDHpPqvmrsaDYzpvo5ayFdxk1yLI0JQtsyidOelFcovrwfvRhHHqGso 9U3g== X-Gm-Message-State: ALoCoQlFACHdYUNFJpsRo0tVEhuNgnMTl56UzWxgm03qeBbAZpw1vJQNZhHl+2NAw0J7JSQnLQ1x X-Received: by 10.236.35.71 with SMTP id t47mr1946615yha.72.1385727614194; Fri, 29 Nov 2013 04:20:14 -0800 (PST) Received: from localhost.localdomain (cpc15-aztw25-2-0-cust493.aztw.cable.virginm.net. [92.233.57.238]) by mx.google.com with ESMTPSA id m29sm101911689yho.14.2013.11.29.04.20.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Nov 2013 04:20:13 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dwmw2@infradead.org Subject: [PATCH v3 20/36] mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing mode Date: Fri, 29 Nov 2013 12:19:09 +0000 Message-Id: <1385727565-25794-21-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1385727565-25794-1-git-send-email-lee.jones@linaro.org> References: <1385727565-25794-1-git-send-email-lee.jones@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131129_042036_989136_22BC561C X-CRM114-Status: UNSURE ( 9.84 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.213.51 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record Cc: angus.clark@st.com, linus.walleij@linaro.org, Lee Jones , linux-mtd@lists.infradead.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Most Serial Flash chips support 24bit addressing as a default but more recent incarnations can support 32bit. Based on information provided though platform specific data and capabilities we can determine whether or not our current chip can. This patch provides a means to setup the FSM message sequence to put the chip into 32bit mode. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 4edd3f2..325fd7a 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -28,6 +28,8 @@ #include "st_spi_fsm.h" #include "serial_flash_cmds.h" +static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ + static struct stfsm_seq stfsm_seq_read_jedec = { .data_size = TRANSFER_SIZE(8), .seq_opc[0] = (SEQ_OPC_PADS_1 | @@ -170,6 +172,23 @@ static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, } } +static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) +{ + struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr; + uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; + + seq->seq_opc[0] = (SEQ_OPC_PADS_1 | + SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(cmd) | + SEQ_OPC_CSDEASSERT); + + stfsm_load_seq(fsm, seq); + + stfsm_wait_seq(fsm); + + return 0; +} + /* * SoC reset on 'boot-from-spi' systems *