@@ -86,7 +86,7 @@ typedef struct DisasContext {
int override; /* -1 if no override */
int prefix;
TCGMemOp aflag;
- int dflag;
+ TCGMemOp dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
@@ -296,6 +296,40 @@ static inline bool byte_reg_is_xH(int reg)
return true;
}
+/* Select the size of a push/pop operation. */
+static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
+{
+ if (CODE64(s)) {
+ return ot == MO_16 ? MO_16 : MO_64;
+ } else {
+ return ot;
+ }
+}
+
+/* Select only size 64 else 32. Used for SSE operand sizes. */
+static inline TCGMemOp mo_64_32(TCGMemOp ot)
+{
+#ifdef TARGET_X86_64
+ return ot == MO_64 ? MO_64 : MO_32;
+#else
+ return MO_32;
+#endif
+}
+
+/* Select size 8 if lsb of B is clear, else OT. Used for decoding
+ byte vs word opcodes. */
+static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)
+{
+ return b & 1 ? ot : MO_8;
+}
+
+/* Select size 8 if lsb of B is clear, else OT capped at 32.
+ Used for decoding operand size of port opcodes. */
+static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)
+{
+ return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;
+}
+
static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
{
switch(ot) {
@@ -2357,7 +2391,7 @@ static void gen_push_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
+ if (s->dflag != MO_16) {
gen_op_addq_A0_im(-8);
gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
} else {
@@ -2369,10 +2403,7 @@ static void gen_push_T0(DisasContext *s)
#endif
{
gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
+ gen_op_addl_A0_im(-1 << s->dflag);
if (s->ss32) {
if (s->addseg) {
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2383,7 +2414,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(MO_32, R_ESP);
else
@@ -2398,7 +2429,7 @@ static void gen_push_T1(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
+ if (s->dflag != MO_16) {
gen_op_addq_A0_im(-8);
gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
@@ -2410,10 +2441,7 @@ static void gen_push_T1(DisasContext *s)
#endif
{
gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
+ gen_op_addl_A0_im(-1 << s->dflag);
if (s->ss32) {
if (s->addseg) {
gen_op_addl_A0_seg(s, R_SS);
@@ -2422,12 +2450,12 @@ static void gen_push_T1(DisasContext *s)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
+ gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(MO_32, R_ESP);
else
- gen_stack_update(s, (-2) << s->dflag);
+ gen_stack_update(s, -1 << s->dflag);
}
}
@@ -2437,7 +2465,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0);
} else
#endif
{
@@ -2449,20 +2477,13 @@ static void gen_pop_T0(DisasContext *s)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
}
}
static void gen_pop_update(DisasContext *s)
{
-#ifdef TARGET_X86_64
- if (CODE64(s) && s->dflag) {
- gen_stack_update(s, 8);
- } else
-#endif
- {
- gen_stack_update(s, 2 << s->dflag);
- }
+ gen_stack_update(s, 1 << mo_pushpop(s, s->dflag));
}
static void gen_stack_A0(DisasContext *s)
@@ -2480,7 +2501,7 @@ static void gen_pusha(DisasContext *s)
{
int i;
gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-16 << s->dflag);
+ gen_op_addl_A0_im(-8 << s->dflag);
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2488,8 +2509,8 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
@@ -2502,31 +2523,28 @@ static void gen_popa(DisasContext *s)
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
+ tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_mov_reg_T0(s->dflag, 7 - i);
}
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_addl_A0_im(1 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- TCGMemOp ot;
- int opsize;
+ TCGMemOp ot = mo_pushpop(s, s->dflag);
+ int opsize = 1 << ot;
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
- ot = s->dflag ? MO_64 : MO_16;
- opsize = 1 << ot;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addq_A0_im(-opsize);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2546,9 +2564,6 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
} else
#endif
{
- ot = s->dflag + MO_16;
- opsize = 2 << s->dflag;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
@@ -2562,7 +2577,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32(s->dflag),
+ tcg_const_i32(s->dflag - 1),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
@@ -3136,7 +3151,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
} else
@@ -3151,7 +3166,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x16e: /* movd xmm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
@@ -3316,7 +3331,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x7e: /* movd ea, mm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
@@ -3330,7 +3345,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x17e: /* movd ea, xmm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
@@ -3500,7 +3515,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22a: /* cvtsi2ss */
case 0x32a: /* cvtsi2sd */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
@@ -3552,7 +3567,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32c: /* cvttsd2si */
case 0x22d: /* cvtss2si */
case 0x32d: /* cvtsd2si */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) {
@@ -3602,7 +3617,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1c5:
if (mod != 3)
goto illegal_op;
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3755,7 +3770,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
if ((b & 0xff) == 0xf0) {
ot = MO_8;
- } else if (s->dflag != 2) {
+ } else if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
@@ -3766,7 +3781,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_op_mov_reg_T0(ot, reg);
break;
@@ -3784,7 +3799,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {
goto illegal_op;
}
- if (s->dflag != 2) {
+ if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
@@ -3807,7 +3822,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
gen_op_mov_reg_T0(ot, reg);
@@ -3821,7 +3836,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
{
TCGv bound, zero;
@@ -3861,7 +3876,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
{
@@ -3888,7 +3903,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
@@ -3914,11 +3929,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
@@ -3932,11 +3947,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
@@ -3952,7 +3967,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
TCGv carry_in, carry_out, zero;
int end_op;
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
@@ -4031,7 +4046,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (ot == MO_64) {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
@@ -4063,7 +4078,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
@@ -4120,7 +4135,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
if (sse_fn_eppi == SSE_SPECIAL) {
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
gen_lea_modrm(env, s, modrm);
@@ -4278,7 +4293,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
set_cc_op(s, CC_OP_EFLAGS);
- if (s->dflag == 2)
+ if (s->dflag == MO_64)
/* The helper must use entire 64-bit gp registers */
val |= 1 << 8;
}
@@ -4301,7 +4316,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
if (ot == MO_64) {
@@ -4432,9 +4447,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
- int b, prefixes, dflag;
+ int b, prefixes;
int shift;
- TCGMemOp ot, aflag;
+ TCGMemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4570,14 +4585,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* In 64-bit mode, the default data size is 32-bit. Select 64-bit
data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
over 0x66 if both are present. */
- dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
- dflag = s->code32;
- if (prefixes & PREFIX_DATA) {
- dflag ^= 1;
+ if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {
+ dflag = MO_32;
+ } else {
+ dflag = MO_16;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
@@ -4619,10 +4635,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = (b >> 3) & 7;
f = (b >> 1) & 3;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch(f) {
case 0: /* OP Ev, Gv */
@@ -4679,10 +4692,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int val;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4719,19 +4729,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4927,10 +4934,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4944,10 +4948,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* operand size for jumps is 64 bit */
ot = MO_64;
} else if (op == 3 || op == 5) {
- ot = dflag ? MO_32 + (rex_w == 1) : MO_16;
+ ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
- ot = dflag ? MO_64 : MO_16;
+ ot = mo_pushpop(s, dflag);
}
}
if (mod != 3) {
@@ -4975,7 +4979,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
next_eip = s->pc - s->cs_base;
@@ -4994,18 +4998,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - pc_start));
} else {
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
}
gen_eob(s);
break;
case 4: /* jmp Ev */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -5039,10 +5043,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x84: /* test Ev, Gv */
case 0x85:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5055,10 +5056,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa8: /* test eAX, Iv */
case 0xa9:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
@@ -5068,47 +5066,57 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x98: /* CWDE/CBW */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ case MO_64:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_64, R_EAX);
- } else
+ break;
#endif
- if (dflag == 1) {
+ case MO_32:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_32, R_EAX);
- } else {
+ break;
+ case MO_16:
gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_16, R_EAX);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x99: /* CDQ/CWD */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ case MO_64:
gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
gen_op_mov_reg_T0(MO_64, R_EDX);
- } else
+ break;
#endif
- if (dflag == 1) {
+ case MO_32:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
gen_op_mov_reg_T0(MO_32, R_EDX);
- } else {
+ break;
+ case MO_16:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
gen_op_mov_reg_T0(MO_16, R_EDX);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
if (b == 0x69)
@@ -5160,10 +5168,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5191,10 +5196,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
int label1, label2;
TCGv t0, t1, t2, a0;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5250,7 +5252,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if ((mod == 3) || ((modrm & 0x38) != 0x8))
goto illegal_op;
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
@@ -5277,11 +5279,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_T0(s);
break;
case 0x58 ... 0x5f: /* pop */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s);
@@ -5299,11 +5297,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x68: /* push Iv */
case 0x6a:
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
if (b == 0x68)
val = insn_get(env, s, ot);
else
@@ -5312,11 +5306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
gen_pop_T0(s);
@@ -5355,11 +5345,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(MO_16, R_ESP);
}
gen_pop_T0(s);
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
gen_op_mov_reg_T0(ot, R_EBP);
gen_pop_update(s);
break;
@@ -5414,10 +5400,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* mov */
case 0x88:
case 0x89: /* mov Gv, Ev */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5426,10 +5409,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xc6:
case 0xc7: /* mov Ev, Iv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod != 3) {
@@ -5446,10 +5426,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = MO_16 + dflag;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5483,10 +5460,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (reg >= 6)
goto illegal_op;
gen_op_movl_T0_seg(reg);
- if (mod == 3)
- ot = MO_16 + dflag;
- else
- ot = MO_16;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -5499,7 +5473,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGMemOp s_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
/* ot is the size of source */
ot = (b & 1) + MO_8;
/* s_ot is the sign+size of source */
@@ -5537,7 +5511,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8d: /* lea */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -5559,10 +5533,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
target_ulong offset_addr;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch (s->aflag) {
#ifdef TARGET_X86_64
case MO_64:
@@ -5601,7 +5572,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
uint64_t tmp;
/* 64 bit case */
tmp = cpu_ldq_code(env, s->pc);
@@ -5612,7 +5583,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else
#endif
{
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
@@ -5622,16 +5593,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
- ot = dflag + MO_16;
+ ot = dflag;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5672,7 +5640,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5700,11 +5668,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
shift = 2;
grp2:
{
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
@@ -5757,7 +5721,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = 1;
shift = 0;
do_shiftd:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -5921,7 +5885,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0c: /* fldenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
@@ -5931,7 +5895,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0e: /* fnstenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
@@ -5952,12 +5916,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2c: /* frstor mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2e: /* fnsave mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
@@ -6304,11 +6268,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa4: /* movsS */
case 0xa5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6318,11 +6278,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xaa: /* stosS */
case 0xab:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6331,10 +6287,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xac: /* lodsS */
case 0xad:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6343,10 +6296,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xae: /* scasS */
case 0xaf:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6358,10 +6308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa6: /* cmpsS */
case 0xa7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6372,10 +6319,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x6c: /* insS */
case 0x6d:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
@@ -6390,10 +6334,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x6e: /* outsS */
case 0x6f:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
@@ -6412,10 +6353,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe4:
case 0xe5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6431,10 +6369,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xe6:
case 0xe7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6452,10 +6387,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xec:
case 0xed:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6471,10 +6403,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xee:
case 0xef:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6497,10 +6426,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
gen_pop_T0(s);
- if (CODE64(s) && s->dflag)
- s->dflag = 2;
- gen_stack_update(s, val + (2 << s->dflag));
- if (s->dflag == 0) {
+ if (CODE64(s) && dflag != MO_16) {
+ dflag = MO_64;
+ }
+ gen_stack_update(s, val + (1 << dflag));
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -6509,7 +6439,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc3: /* ret */
gen_pop_T0(s);
gen_pop_update(s);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -6522,21 +6452,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_T0();
/* pop selector */
- gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << dflag);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
- gen_stack_update(s, val + (4 << s->dflag));
+ gen_stack_update(s, val + (2 << dflag));
}
gen_eob(s);
break;
@@ -6547,19 +6477,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
if (!s->pe) {
/* real mode */
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
} else if (s->vm86) {
if (s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
}
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
set_cc_op(s, CC_OP_EFLAGS);
}
@@ -6567,16 +6497,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xe8: /* call im */
{
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
tcg_gen_movi_tl(cpu_T[0], next_eip);
gen_push_T0(s);
gen_jmp(s, tval);
@@ -6588,7 +6520,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
@@ -6597,15 +6529,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
goto do_lcall;
case 0xe9: /* jmp im */
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
gen_jmp(s, tval);
break;
case 0xea: /* ljmp im */
@@ -6614,7 +6548,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
@@ -6625,15 +6559,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xeb: /* jmp Jb */
tval = (int8_t)insn_get(env, s, MO_8);
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jmp(s, tval);
break;
case 0x70 ... 0x7f: /* jcc Jb */
tval = (int8_t)insn_get(env, s, MO_8);
goto do_jcc;
case 0x180 ... 0x18f: /* jcc Jv */
- if (dflag) {
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
} else {
tval = (int16_t)insn_get(env, s, MO_16);
@@ -6641,8 +6576,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
do_jcc:
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jcc(s, b, tval, next_eip);
break;
@@ -6655,7 +6591,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_cmovcc1(env, s, ot, b, modrm, reg);
@@ -6680,7 +6616,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_pop_T0(s);
if (s->cpl == 0) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
@@ -6695,7 +6631,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
} else {
if (s->cpl <= s->iopl) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK |
AC_MASK |
@@ -6712,7 +6648,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
& 0xffff));
}
} else {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)));
@@ -6772,7 +6708,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -6803,7 +6739,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1bb: /* btc */
op = 3;
do_btx:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -6861,7 +6797,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
@@ -7060,7 +6996,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7079,7 +7015,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_64, reg);
@@ -7109,7 +7045,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16)
tval &= 0xffff;
l1 = gen_new_label();
@@ -7195,7 +7131,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
+ gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
gen_eob(s);
}
break;
@@ -7213,7 +7149,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (s->lma) {
set_cc_op(s, CC_OP_EFLAGS);
@@ -7247,9 +7183,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
@@ -7270,9 +7204,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
@@ -7320,7 +7252,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7376,7 +7308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7477,7 +7409,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
if (op == 2) {
@@ -7580,7 +7512,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -7654,7 +7586,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
@@ -7790,7 +7722,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -7815,7 +7747,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 1: /* fxrstor */
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
@@ -7828,8 +7760,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxrstor(cpu_env, cpu_A0,
- tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxrstor(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 2: /* ldmxcsr */
case 3: /* stmxcsr */
@@ -7899,12 +7830,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
- if (s->prefix & PREFIX_DATA)
+ if (s->prefix & PREFIX_DATA) {
ot = MO_16;
- else if (s->dflag != 2)
- ot = MO_32;
- else
- ot = MO_64;
+ } else {
+ ot = mo_64_32(dflag);
+ }
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
Changing the domain to TCGMemOp makes it easier to interoperate with other portions of the rest of the translator. We now only have one domain for size operands inside the translator, which makes things less confusing all the way around. There are still a number of helpers that continue to use the log2-1 domain. Signed-off-by: Richard Henderson <rth@twiddle.net> --- target-i386/translate.c | 498 +++++++++++++++++++++--------------------------- 1 file changed, 214 insertions(+), 284 deletions(-)