| Message ID | 000101ceea5e$8207ae90$86170bb0$@arm.com |
|---|---|
| State | New |
| Headers | show |
On 26/11/13 04:18, Terry Guo wrote: > Hi, > > This patch intends to fix ICE when high register is used for pic base > register for thumb1 target. Tested with gcc regression test, no new > regressions. Is it OK to trunk? > > BR, > Terry > > gcc/ChangeLog: > > 2013-11-26 Terry Guo <terry.guo@arm.com> > > * config/arm/arm.c (require_pic_register): Handle high pic base > register for > thumb-1. > (arm_load_pic_register): Also initialize high pic base register. > * doc/invoke.texi: Update documentation for option -mpic-register. > > gcc/testsuite/ChangeLog: > > 2013-11-26 Terry Guo <terry.guo@arm.com> > > * gcc.target/arm/thumb1-pic-high.c: New case. > * gcc.target/arm/thumb1-pic-single-base.c: New case. > > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 501d080..f0b46e9 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -12216,8 +12216,11 @@ before execution begins. > > @item -mpic-register=@var{reg} > @opindex mpic-register > -Specify the register to be used for PIC addressing. The default is R10 > -unless stack-checking is enabled, when R9 is used. > +Specify the register to be used for PIC addressing. > +For standard PIC base case, the default will be any suitable register > +determined by compiler. For single PIC base case, the default is R9 > +if target is EABI based or stack-checking is enabled, otherwise > +the default is R10. > Please can you put @samp{<reg>} around the uses of R9 and R10. Otherwise, OK. R.
> -----Original Message----- > From: Richard Earnshaw > Sent: Tuesday, November 26, 2013 5:44 PM > To: Terry Guo > Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org > Subject: Re: [Patch, ARM] Fix ICE when high register is used as pic base > register for thumb1 target > > On 26/11/13 04:18, Terry Guo wrote: > > Hi, > > > > This patch intends to fix ICE when high register is used for pic base > > register for thumb1 target. Tested with gcc regression test, no new > > regressions. Is it OK to trunk? > > > > BR, > > Terry > > > > gcc/ChangeLog: > > > > 2013-11-26 Terry Guo <terry.guo@arm.com> > > > > * config/arm/arm.c (require_pic_register): Handle high pic > > base register for > > thumb-1. > > (arm_load_pic_register): Also initialize high pic base register. > > * doc/invoke.texi: Update documentation for option -mpic-register. > > > > gcc/testsuite/ChangeLog: > > > > 2013-11-26 Terry Guo <terry.guo@arm.com> > > > > * gcc.target/arm/thumb1-pic-high.c: New case. > > * gcc.target/arm/thumb1-pic-single-base.c: New case. > > > > > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index > > 501d080..f0b46e9 100644 > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -12216,8 +12216,11 @@ before execution begins. > > > > @item -mpic-register=@var{reg} > > @opindex mpic-register > > -Specify the register to be used for PIC addressing. The default is > > R10 -unless stack-checking is enabled, when R9 is used. > > +Specify the register to be used for PIC addressing. > > +For standard PIC base case, the default will be any suitable register > > +determined by compiler. For single PIC base case, the default is R9 > > +if target is EABI based or stack-checking is enabled, otherwise the > > +default is R10. > > > > Please can you put @samp{<reg>} around the uses of R9 and R10. > Otherwise, OK. > R. > Thanks Richard. The updated patch is committed to trunk. Is it OK to backport to FSF 4.8 branch as a bug fix? BR, Terry
On 28/11/13 05:55, Terry Guo wrote: > > >> -----Original Message----- >> From: Richard Earnshaw >> Sent: Tuesday, November 26, 2013 5:44 PM >> To: Terry Guo >> Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org >> Subject: Re: [Patch, ARM] Fix ICE when high register is used as pic base >> register for thumb1 target >> >> On 26/11/13 04:18, Terry Guo wrote: >>> Hi, >>> >>> This patch intends to fix ICE when high register is used for pic base >>> register for thumb1 target. Tested with gcc regression test, no new >>> regressions. Is it OK to trunk? >>> >>> BR, >>> Terry >>> >>> gcc/ChangeLog: >>> >>> 2013-11-26 Terry Guo <terry.guo@arm.com> >>> >>> * config/arm/arm.c (require_pic_register): Handle high pic >>> base register for >>> thumb-1. >>> (arm_load_pic_register): Also initialize high pic base register. >>> * doc/invoke.texi: Update documentation for option > -mpic-register. >>> >>> gcc/testsuite/ChangeLog: >>> >>> 2013-11-26 Terry Guo <terry.guo@arm.com> >>> >>> * gcc.target/arm/thumb1-pic-high.c: New case. >>> * gcc.target/arm/thumb1-pic-single-base.c: New case. >>> >>> >>> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index >>> 501d080..f0b46e9 100644 >>> --- a/gcc/doc/invoke.texi >>> +++ b/gcc/doc/invoke.texi >>> @@ -12216,8 +12216,11 @@ before execution begins. >>> >>> @item -mpic-register=@var{reg} >>> @opindex mpic-register >>> -Specify the register to be used for PIC addressing. The default is >>> R10 -unless stack-checking is enabled, when R9 is used. >>> +Specify the register to be used for PIC addressing. >>> +For standard PIC base case, the default will be any suitable register >>> +determined by compiler. For single PIC base case, the default is R9 >>> +if target is EABI based or stack-checking is enabled, otherwise the >>> +default is R10. >>> >> >> Please can you put @samp{<reg>} around the uses of R9 and R10. >> Otherwise, OK. >> R. >> > > Thanks Richard. The updated patch is committed to trunk. Is it OK to > backport to FSF 4.8 branch as a bug fix? > Yes. R.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dc3dbdb..4af6c05 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -5917,7 +5917,8 @@ require_pic_register (void) if (!crtl->uses_pic_offset_table) { gcc_assert (can_create_pseudo_p ()); - if (arm_pic_register != INVALID_REGNUM) + if (arm_pic_register != INVALID_REGNUM + && !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM)) { if (!cfun->machine->pic_reg) cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); @@ -5943,7 +5944,12 @@ require_pic_register (void) crtl->uses_pic_offset_table = 1; start_sequence (); - arm_load_pic_register (0UL); + if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM + && arm_pic_register > LAST_LO_REGNUM) + emit_move_insn (cfun->machine->pic_reg, + gen_rtx_REG (Pmode, arm_pic_register)); + else + arm_load_pic_register (0UL); seq = get_insns (); end_sequence (); @@ -6202,6 +6208,14 @@ arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); } + else if (arm_pic_register != INVALID_REGNUM + && arm_pic_register > LAST_LO_REGNUM + && REGNO (pic_reg) <= LAST_LO_REGNUM) + { + emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); + emit_move_insn (gen_rtx_REG (Pmode, arm_pic_register), pic_reg); + emit_use (gen_rtx_REG (Pmode, arm_pic_register)); + } else emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); } diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 501d080..f0b46e9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12216,8 +12216,11 @@ before execution begins. @item -mpic-register=@var{reg} @opindex mpic-register -Specify the register to be used for PIC addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for PIC addressing. +For standard PIC base case, the default will be any suitable register +determined by compiler. For single PIC base case, the default is R9 +if target is EABI based or stack-checking is enabled, otherwise +the default is R10. @item -mpic-data-is-text-relative @opindex mpic-data-is-text-relative diff --git a/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c b/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c new file mode 100644 index 0000000..df269fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-mthumb -fpic -mpic-register=9" } */ + +int g_test; + +int +foo (int par) +{ + g_test = par; +} diff --git a/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c b/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c new file mode 100644 index 0000000..6e9b257 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-mthumb -fpic -msingle-pic-base" } */ + +int g_test; + +int +foo (int par) +{ + g_test = par; +}
Hi, This patch intends to fix ICE when high register is used for pic base register for thumb1 target. Tested with gcc regression test, no new regressions. Is it OK to trunk? BR, Terry gcc/ChangeLog: 2013-11-26 Terry Guo <terry.guo@arm.com> * config/arm/arm.c (require_pic_register): Handle high pic base register for thumb-1. (arm_load_pic_register): Also initialize high pic base register. * doc/invoke.texi: Update documentation for option -mpic-register. gcc/testsuite/ChangeLog: 2013-11-26 Terry Guo <terry.guo@arm.com> * gcc.target/arm/thumb1-pic-high.c: New case. * gcc.target/arm/thumb1-pic-single-base.c: New case. From 44dc01379291b53d6eeb227d7006d3541e27dd93 Mon Sep 17 00:00:00 2001 From: Terry Guo <terry.guo@arm.com> Date: Tue, 26 Nov 2013 10:10:50 +0800 Subject: [PATCH] pic v6 --- gcc/config/arm/arm.c | 18 ++++++++++++++++-- gcc/doc/invoke.texi | 7 +++++-- gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c | 11 +++++++++++ .../gcc.target/arm/thumb1-pic-single-base.c | 11 +++++++++++ 4 files changed, 43 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c