diff mbox

PATCH: Document POPCNT and enable it for Silvermont

Message ID 20131122025203.GA26544@intel.com
State New
Headers show

Commit Message

H.J. Lu Nov. 22, 2013, 2:52 a.m. UTC 
Hi,

Silvermont supports POPCNT.  This patch enables POPCNT for Silvermont.
I also documented POPCNT for corei7, corei7-avx, core-avx-i, core-avx2 and
slm.  Since POPCNT is enabled with -msse4.2, this patch doesn't change
code generation.  It just makes it clear.  OK to install?

Thanks.

H.J.
----
2013-11-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (processor_alias_table): Enable PTA_POPCNT
	for Silvermont.

	* doc/invoke.texi: Mention POPCNT for corei7, corei7-avx,
	core-avx-i, core-avx2 and slm.

Comments

Uros Bizjak Nov. 22, 2013, 7:30 a.m. UTC | #1 
On Fri, Nov 22, 2013 at 3:52 AM, H.J. Lu <hongjiu.lu@intel.com> wrote:

> Silvermont supports POPCNT.  This patch enables POPCNT for Silvermont.
> I also documented POPCNT for corei7, corei7-avx, core-avx-i, core-avx2 and
> slm.  Since POPCNT is enabled with -msse4.2, this patch doesn't change
> code generation.  It just makes it clear.  OK to install?
>
> Thanks.
>
> H.J.
> ----
> 2013-11-21  H.J. Lu  <hongjiu.lu@intel.com>
>
>         * config/i386/i386.c (processor_alias_table): Enable PTA_POPCNT
>         for Silvermont.
>
>         * doc/invoke.texi: Mention POPCNT for corei7, corei7-avx,
>         core-avx-i, core-avx2 and slm.

OK.

Thanks,
Uros.
diff mbox

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 749be7f..b167217 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3136,8 +3136,8 @@  ix86_option_override_internal (bool main_args_p,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
       {"slm", PROCESSOR_SLM, CPU_SLM,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_MOVBE
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_MOVBE
 	| PTA_FXSR},
       {"geode", PROCESSOR_GEODE, CPU_GEODE,
 	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6fc56b9..fe787d3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14512,22 +14512,22 @@  Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
 
 @item corei7
-Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1
-and SSE4.2 instruction set support.
+Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2 and POPCNT instruction set support.
 
 @item corei7-avx
 Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, AVX, AES and PCLMUL instruction set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
 
 @item core-avx-i
 Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction
-set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
+instruction set support.
 
 @item core-avx2
 Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2
-and F16C instruction set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2 and F16C instruction set support.
 
 @item atom
 Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
@@ -14535,7 +14535,7 @@  instruction set support.
 
 @item slm
 Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1 and SSE4.2 instruction set support.
+SSE4.1, SSE4.2 and POPCNT instruction set support.
 
 @item k6
 AMD K6 CPU with MMX instruction set support.