diff mbox

[4/4] Conform vector implementation to ABI -- narrowing operations.

Message ID 528E0E0F.9040808@arm.com
State New
Headers show

Commit Message

Tejas Belagod Nov. 21, 2013, 1:43 p.m. UTC 
Hi,

The attached patch swaps around high and low bits of the source operands of 
narrow patterns for big-endian so that they end up in the correct order in the 
destination.

Tested for aarch64-none-elf and aarch64_be-none-elf. OK for trunk?

Thanks,
Tejas Belagod
ARM.

2013-11-21  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
	vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for big-endian.

Comments

Marcus Shawcroft Nov. 22, 2013, 9:30 a.m. UTC | #1 
On 21 November 2013 13:43, Tejas Belagod <tbelagod@arm.com> wrote:
>
> Hi,
>
> The attached patch swaps around high and low bits of the source operands of
> narrow patterns for big-endian so that they end up in the correct order in
> the destination.
>
> Tested for aarch64-none-elf and aarch64_be-none-elf. OK for trunk?
>
> Thanks,
> Tejas Belagod
> ARM.
>
> 2013-11-21  Tejas Belagod  <tejas.belagod@arm.com>
>
> gcc/
>         * config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
>         vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for
> big-endian.

OK

/Marcus
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b9ebdf5..c802a27 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -891,9 +891,11 @@ 
  "TARGET_SIMD"
 {
   rtx tempreg = gen_reg_rtx (<VDBL>mode);
+  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
+  int hi = BYTES_BIG_ENDIAN ? 1 : 2;
 
-  emit_insn (gen_move_lo_quad_<Vdbl> (tempreg, operands[1]));
-  emit_insn (gen_move_hi_quad_<Vdbl> (tempreg, operands[2]));
+  emit_insn (gen_move_lo_quad_<Vdbl> (tempreg, operands[lo]));
+  emit_insn (gen_move_hi_quad_<Vdbl> (tempreg, operands[hi]));
   emit_insn (gen_aarch64_simd_vec_pack_trunc_<Vdbl> (operands[0], tempreg));
   DONE;
 })
@@ -906,7 +908,12 @@ 
 	 (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w"))
 	 (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))]
  "TARGET_SIMD"
- "xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>"
+ {
+   if (BYTES_BIG_ENDIAN)
+     return "xtn\\t%0.<Vntype>, %2.<Vtype>\;xtn2\\t%0.<V2ntype>, %1.<Vtype>";
+   else
+     return "xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>";
+ }
   [(set_attr "type" "multiple")
    (set_attr "length" "8")]
 )
@@ -1444,9 +1451,12 @@ 
   "TARGET_SIMD"
   {
     rtx tmp = gen_reg_rtx (V2SFmode);
-    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[1]));
+    int lo = BYTES_BIG_ENDIAN ? 2 : 1;
+    int hi = BYTES_BIG_ENDIAN ? 1 : 2;
+
+    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo]));
     emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0],
-						   tmp, operands[2]));
+						   tmp, operands[hi]));
     DONE;
   }
 )
@@ -1462,8 +1472,11 @@ 
   "TARGET_SIMD"
   {
     rtx tmp = gen_reg_rtx (V2SFmode);
-    emit_insn (gen_move_lo_quad_v2df (tmp, operands[1]));
-    emit_insn (gen_move_hi_quad_v2df (tmp, operands[2]));
+    int lo = BYTES_BIG_ENDIAN ? 2 : 1;
+    int hi = BYTES_BIG_ENDIAN ? 1 : 2;
+
+    emit_insn (gen_move_lo_quad_v2df (tmp, operands[lo]));
+    emit_insn (gen_move_hi_quad_v2df (tmp, operands[hi]));
     emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp));
     DONE;
   }