From patchwork Wed Nov 20 17:19:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 292836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 314352C012D for ; Thu, 21 Nov 2013 04:22:15 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; q=dns; s=default; b=M7YVcwsTUK0vbnQ5 TJHS+Nl2n9cY+O2Ugo+VGs7Jbbdoy58sakxsSeTtXb6HzG/ZPN5xNMgx+GW9WLBN lEfA9p38c7+vfu8GZOhW63U1iqJ6dK9JyA5xzMdpXIIGlyA//Djde+nQdk0whGtf PP6xAcXiDgUydqEQ8VDxCPgoIqo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; s=default; bh=/x5BYZg0vKdZ9L73MuHQ/r MTpBM=; b=aIK3t5LS/Ag/aWSACQJ3e7/CbdxnN7hjBnDKs8pCERCkwwn62G5iwi d3m1utTkwBKWmKdryjhdM0Bg2ASapFd1ZAiS5UgRgzOqJkMX/sGTUY4+7Fn4O6Hs WCsxX6SdWJZ/z+w2Sme3twwiKjQsKNo87ydGnEXYN0vqK6K4DO93g= Received: (qmail 3926 invoked by alias); 20 Nov 2013 17:21:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3893 invoked by uid 89); 20 Nov 2013 17:21:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=AWL, BAYES_50, RDNS_NONE, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: relay1.mentorg.com Received: from Unknown (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 20 Nov 2013 17:20:07 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1VjBRP-0001he-QP from Maciej_Rozycki@mentor.com ; Wed, 20 Nov 2013 09:19:51 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 20 Nov 2013 09:19:51 -0800 Received: from [172.30.64.178] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.2.247.3; Wed, 20 Nov 2013 17:19:50 +0000 Date: Wed, 20 Nov 2013 17:19:44 +0000 From: "Maciej W. Rozycki" To: Richard Sandiford CC: Sanjay Patel , Steve Ellcey , Subject: Re: [PATCH] MIPS: MIPS32r2 FP indexed access instruction set support In-Reply-To: <87eh6gd9bj.fsf@talisman.default> Message-ID: References: <87eh6gd9bj.fsf@talisman.default> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 On Sat, 16 Nov 2013, Richard Sandiford wrote: > So the reasoning is that, after your RECIP.fmt patch, the only direct uses > of ISA_HAS_FP4 for instruction selection are indexed loads and stores. > That's why extending them to ISA_MIPS32R2 && !TARGET_FLOAT64 allows > ISA_HAS_FP4 to be simplified. But if we keep: > > > @@ -906,16 +906,14 @@ struct mips_cpu_info { > > #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) > > > > /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ > > -#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ > > - || (ISA_MIPS32R2 && !TARGET_MIPS16)) > > +#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 > > > > /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ > > #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF > > > > /* ISA has floating-point nmadd and nmsub instructions > > 'd = -((a * b) [+-] c)'. */ > > -#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ > > - || (ISA_MIPS32R2 && !TARGET_MIPS16)) > > +#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4 > > then I think we should also have a macro like: > > /* ISA has indexed floating-point loads and stores (LWXC1, LDXC1, SWXC1 > and SDXC1). */ > #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 > > and add: > > Note that this macro should only be used by other ISA_HAS_* macros. > > to the ISA_HAS_FP4 comment. Agreed, it makes sense to me indeed. > OK with those changes, thanks. This is the final change I have applied. I have verified that it still makes the desired effect and successfully retested it for mips-linux-gnu, o32 ABI. Thanks for your review. 2013-11-20 Maciej W. Rozycki gcc/ * config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64 restriction for ISA_MIPS32R2. (ISA_HAS_LXC1_SXC1): New macro. (ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing. (ISA_HAS_NMADD4_NMSUB4): Likewise. (ISA_HAS_FP_RECIP_RSQRT): Likewise. (ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4. * config/mips/mips.md (*_): Use ISA_HAS_LXC1_SXC1 rather than ISA_HAS_FP4. (*_): Likewise. Maciej gcc-mips32r2-index.patch Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.h =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.h 2013-11-19 02:01:22.000000000 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.h 2013-11-19 02:14:49.678712529 +0000 @@ -882,13 +882,18 @@ struct mips_cpu_info { /* This is a catch all for other mips4 instructions: indexed load, the FP madd and msub instructions, and the FP recip and recip sqrt - instructions. */ + instructions. Note that this macro should only be used by other + ISA_HAS_* macros. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && TARGET_FLOAT64) \ + || ISA_MIPS32R2 \ || ISA_MIPS64 \ || ISA_MIPS64R2) \ && !TARGET_MIPS16) +/* ISA has floating-point indexed load and store instructions + (LWXC1, LDXC1, SWXC1 and SDXC1). */ +#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 + /* ISA has paired-single instructions. */ #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) @@ -906,16 +911,14 @@ struct mips_cpu_info { #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ -#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) +#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF /* ISA has floating-point nmadd and nmsub instructions 'd = -((a * b) [+-] c)'. */ -#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) +#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4 /* ISA has floating-point nmadd and nmsub instructions 'c = -((a * b) [+-] c)'. */ @@ -926,7 +929,7 @@ struct mips_cpu_info { doubles are stored in pairs of FPRs, so for safety's sake, we apply this restriction to the MIPS IV ISA too. */ #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ - ((((ISA_HAS_FP4 || ISA_MIPS32R2) \ + (((ISA_HAS_FP4 \ && ((MODE) == SFmode \ || ((TARGET_FLOAT64 \ || ISA_MIPS32R2 \ @@ -1006,11 +1009,7 @@ struct mips_cpu_info { 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_PREFETCHX ISA_HAS_FP4 /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.md =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.md 2013-11-19 01:48:25.000000000 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.md 2013-11-19 02:16:04.188764680 +0000 @@ -4440,7 +4440,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") (match_operand:P 2 "register_operand" "d"))))] - "ISA_HAS_FP4" + "ISA_HAS_LXC1_SXC1" "\t%0,%1(%2)" [(set_attr "type" "fpidxload") (set_attr "mode" "")]) @@ -4449,7 +4449,7 @@ [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") (match_operand:P 2 "register_operand" "d"))) (match_operand:ANYF 0 "register_operand" "f"))] - "ISA_HAS_FP4" + "ISA_HAS_LXC1_SXC1" "\t%0,%1(%2)" [(set_attr "type" "fpidxstore") (set_attr "mode" "")])