Message ID | 1384879786-6721-1-git-send-email-pbonzini@redhat.com |
---|---|
State | New |
Headers | show |
On Tue, Nov 19, 2013 at 05:49:46PM +0100, Paolo Bonzini wrote: > Commit 787aaf5 (target-i386: forward CPUID cache leaves when -cpu host is > used, 2013-09-02) brings bits 31..26 of CPUID leaf 04h out of sync with > the APIC IDs that QEMU reserves for each package. This number must come > from "-smp" options rather than from the host CPUID. > > It also turns out that this unsyncing makes Windows Server 2012R2 fail > to boot. > > Tested-by: Peter Lieven <pl@kamp.de> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Probably bits 25-14 of EAX will also look funny depending on the requested VCPU topology, but I don't think we need/can do magic there to guess how the cache topology should look like if the configured VCPU topology is completely different from the host topology. > --- > Resending because the mailing list ate the message. > > target-i386/cpu.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 864c80e..8df6747 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -2086,14 +2086,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > /* cache info: needed for Core compatibility */ > if (cpu->cache_info_passthrough) { > host_cpuid(index, count, eax, ebx, ecx, edx); > - break; > - } > - if (cs->nr_cores > 1) { > - *eax = (cs->nr_cores - 1) << 26; > + *eax &= ~0xFC000000; > } else { > *eax = 0; > - } > - switch (count) { > + switch (count) { > case 0: /* L1 dcache info */ > *eax |= CPUID_4_TYPE_DCACHE | \ > CPUID_4_LEVEL(1) | \ > @@ -2133,6 +2129,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > *ecx = 0; > *edx = 0; > break; > + } > + } > + > + /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ > + if ((*eax & 31) && cs->nr_cores > 1) { > + *eax |= (cs->nr_cores - 1) << 26; > } > break; > case 5: > -- > 1.8.4.2 > >
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 864c80e..8df6747 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2086,14 +2086,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { host_cpuid(index, count, eax, ebx, ecx, edx); - break; - } - if (cs->nr_cores > 1) { - *eax = (cs->nr_cores - 1) << 26; + *eax &= ~0xFC000000; } else { *eax = 0; - } - switch (count) { + switch (count) { case 0: /* L1 dcache info */ *eax |= CPUID_4_TYPE_DCACHE | \ CPUID_4_LEVEL(1) | \ @@ -2133,6 +2129,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx = 0; *edx = 0; break; + } + } + + /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ + if ((*eax & 31) && cs->nr_cores > 1) { + *eax |= (cs->nr_cores - 1) << 26; } break; case 5: