MIPS: MIPS32r2 FP indexed access instruction set support
diff mbox

Message ID alpine.DEB.1.10.1311142232110.21686@tp.orcam.me.uk
State Superseded
Headers show

Commit Message

Maciej W. Rozycki Nov. 14, 2013, 11:20 p.m. UTC
Hi,

 Complementing the recent change to enable FP MADD instructions on 
MIPS32r2 processors in the 32-bit FPR mode (CP0.Status.FR=0) here's one to 
enable FP ordinary indexed memory access (i.e. LWXC1, SWXC1, LDXC1 and 
SDXC1) instructions in that case as well.  Architecture documents have 
been amended to make it unambiguous that these instructions are supported 
in that FPU configuration[1][2].  Note that PREFX is already handled like 
this even though old architecture documents did not allow it.

 My understanding also is only a single implementation of a strict 32-bit 
MIPS32r2 FPU (CP1.FIR.F64=0) has been ever made and that chip actually 
supports these instructions, and no future 32-bit FPUs are supposed to be 
made as the architecture no longer allows it[3][4].

 Please note that these instructions continue being generated for MIPS IV 
ISA processors regardless of the FPR mode selected and continue being 
avoided for original MIPS32 ISA revision processors.  We may consider 
changing that separately (for MIPS32 that is), for the sake of emulated 
code such as under Linux (I believe no MIPS32 original revision FPU 
hardware has been ever made; I'll be happy to get corrected if I am wrong 
though).

 As a side effect a number of macros that rely on ISA_HAS_FP4 can be 
simplified and MIPS32r2 special-casing removed.

 I have regression-tested this change with the mips-linux-gnu target and 
the mips32r2/o32 multilib.  I have also verified that the instructions 
affected were absent across the binaries produced by the testsuite before 
applying this change and present afterwards (at 899 instances across the 
testsuite all these instructions are extensively covered; PREFX is 
covered too).

 OK to apply?

 References:

[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
    Instruction Set", Document Number: MD00086, Revision 5.03, Sept. 9,
    2013

[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 
    Instruction Set, Document Number: MD00582, Revision 5.03, Sept. 9, 
    2013

[3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS32 Architecture", Document Number: MD00082, Revision 5.03, Sept.
    9, 2013

[4] "MIPSR Architecture For Programmers, Volume I-B: Introduction to the 
    microMIPS32 Architecture", Document Number: MD00741, Revision 5.03,
    Sept. 9, 2013

2013-11-14  Maciej W. Rozycki  <macro@codesourcery.com>

	gcc/
	* config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64 
	restriction for ISA_MIPS32R2.
	(ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
	(ISA_HAS_NMADD4_NMSUB4): Likewise.
	(ISA_HAS_FP_RECIP_RSQRT): Likewise.
	(ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.

  Maciej

gcc-mips32r2-index.patch

Comments

Richard Sandiford Nov. 16, 2013, 8:45 a.m. UTC | #1
"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> 2013-11-14  Maciej W. Rozycki  <macro@codesourcery.com>
>
> 	gcc/
> 	* config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64 
> 	restriction for ISA_MIPS32R2.
> 	(ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
> 	(ISA_HAS_NMADD4_NMSUB4): Likewise.
> 	(ISA_HAS_FP_RECIP_RSQRT): Likewise.
> 	(ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.

Nice.

So the reasoning is that, after your RECIP.fmt patch, the only direct uses
of ISA_HAS_FP4 for instruction selection are indexed loads and stores.
That's why extending them to ISA_MIPS32R2 && !TARGET_FLOAT64 allows
ISA_HAS_FP4 to be simplified.  But if we keep:

> @@ -906,16 +906,14 @@ struct mips_cpu_info {
>  #define GENERATE_MADD_MSUB	(TARGET_IMADD && !TARGET_MIPS16)
>  
>  /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'.  */
> -#define ISA_HAS_FP_MADD4_MSUB4  (ISA_HAS_FP4				\
> -				 || (ISA_MIPS32R2 && !TARGET_MIPS16))
> +#define ISA_HAS_FP_MADD4_MSUB4  ISA_HAS_FP4
>  
>  /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'.  */
>  #define ISA_HAS_FP_MADD3_MSUB3  TARGET_LOONGSON_2EF
>  
>  /* ISA has floating-point nmadd and nmsub instructions
>     'd = -((a * b) [+-] c)'.  */
> -#define ISA_HAS_NMADD4_NMSUB4	(ISA_HAS_FP4				\
> -				 || (ISA_MIPS32R2 && !TARGET_MIPS16))
> +#define ISA_HAS_NMADD4_NMSUB4	ISA_HAS_FP4

then I think we should also have a macro like:

/* ISA has indexed floating-point loads and stores (LWXC1, LDXC1, SWXC1
   and SDXC1).  */
#define ISA_HAS_LXC1_SXC1	ISA_HAS_FP4

and add:

   Note that this macro should only be used by other ISA_HAS_* macros.

to the ISA_HAS_FP4 comment.

OK with those changes, thanks.

Richard

Patch
diff mbox

Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.h
===================================================================
--- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.h	2013-11-12 15:33:22.277646941 +0000
+++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.h	2013-11-12 15:33:43.788707112 +0000
@@ -884,7 +884,7 @@  struct mips_cpu_info {
    FP madd and msub instructions, and the FP recip and recip sqrt
    instructions.  */
 #define ISA_HAS_FP4		((ISA_MIPS4				\
-				  || (ISA_MIPS32R2 && TARGET_FLOAT64)	\
+				  || ISA_MIPS32R2			\
 				  || ISA_MIPS64				\
 				  || ISA_MIPS64R2)			\
 				 && !TARGET_MIPS16)
@@ -906,16 +906,14 @@  struct mips_cpu_info {
 #define GENERATE_MADD_MSUB	(TARGET_IMADD && !TARGET_MIPS16)
 
 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'.  */
-#define ISA_HAS_FP_MADD4_MSUB4  (ISA_HAS_FP4				\
-				 || (ISA_MIPS32R2 && !TARGET_MIPS16))
+#define ISA_HAS_FP_MADD4_MSUB4  ISA_HAS_FP4
 
 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'.  */
 #define ISA_HAS_FP_MADD3_MSUB3  TARGET_LOONGSON_2EF
 
 /* ISA has floating-point nmadd and nmsub instructions
    'd = -((a * b) [+-] c)'.  */
-#define ISA_HAS_NMADD4_NMSUB4	(ISA_HAS_FP4				\
-				 || (ISA_MIPS32R2 && !TARGET_MIPS16))
+#define ISA_HAS_NMADD4_NMSUB4	ISA_HAS_FP4
 
 /* ISA has floating-point nmadd and nmsub instructions
    'c = -((a * b) [+-] c)'.  */
@@ -926,8 +924,7 @@  struct mips_cpu_info {
    doubles are stored in pairs of FPRs, so for safety's sake, we apply
    this restriction to the MIPS IV ISA too.  */
 #define ISA_HAS_FP_RECIP_RSQRT(MODE)					\
-				(((ISA_HAS_FP4				\
-				   || (ISA_MIPS32R2 && !TARGET_MIPS16))	\
+				((ISA_HAS_FP4				\
 				  && ((MODE) == SFmode			\
 				      || ((TARGET_FLOAT64		\
 					   || !(ISA_MIPS4		\
@@ -1006,11 +1003,7 @@  struct mips_cpu_info {
    'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
    (prefx is a cop1x instruction, so can only be used if FP is
    enabled.)  */
-#define ISA_HAS_PREFETCHX	((ISA_MIPS4				\
-				  || ISA_MIPS32R2			\
-				  || ISA_MIPS64				\
-				  || ISA_MIPS64R2)			\
-				 && !TARGET_MIPS16)
+#define ISA_HAS_PREFETCHX	ISA_HAS_FP4
 
 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
    instructions.  Both require TARGET_HARD_FLOAT, and trunc.w.d