From patchwork Thu Nov 14 23:19:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 291409 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 990C52C00B3 for ; Fri, 15 Nov 2013 10:20:33 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=DK4gIASoRWp6CXslB8HnAOWyuty9ujn658lvrtB/iUXMcr7PD9 Ob/qqxUmPQWHuLuU0XC2ywV3zz2qUNwg/KgzHYXc97+DxxEmHvFBSuCy+8auiChb fv9X1sIsMz3OeVK+nL8VmOAVJZ45xQU5QqD0b8Ds1qpeB/sSeBIViQWmg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=uoD0EPR4OeKB8fPaLTpPZv8OpM8=; b=V4iJAZ5SUVzzVl/t09rX 1FGzmAjk9f48qCnraLB0naXs8C2wkEyXiSZfgxapHyJaghMz/bStHvZToagecL5O Y2WwobvfvX+c8h4rKCqQ71lapdsd4StmWZHJRj3bjMFE1VSU0Ie26ZKEHpnSyU0p ljXIVKrPE+Wg+cXYIF3Qa9I= Received: (qmail 16237 invoked by alias); 14 Nov 2013 23:20:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16225 invoked by uid 89); 14 Nov 2013 23:20:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=AWL, BAYES_50, RDNS_NONE, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: relay1.mentorg.com Received: from Unknown (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2013 23:20:20 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1Vh6Ci-000226-6y from Maciej_Rozycki@mentor.com ; Thu, 14 Nov 2013 15:20:04 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 14 Nov 2013 15:20:03 -0800 Received: from [172.30.64.11] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.2.247.3; Thu, 14 Nov 2013 23:20:01 +0000 Date: Thu, 14 Nov 2013 23:19:55 +0000 From: "Maciej W. Rozycki" To: Richard Sandiford CC: Sanjay Patel , Steve Ellcey , Subject: [PATCH] MIPS: MIPS32r2 FP reciprocal instruction set support Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Hi, Complementing the recent change to enable FP MADD instructions on MIPS32r2 processors in the 32-bit FPR mode (CP0.Status.FR=0) here's one to enable FP reciprocal instructions (RECIP.fmt and RSQRT.fmt) in that case as well. Architecture documents have been amended to make it unambiguous that these instructions are supported in that FPU configuration[1][2]. My understanding also is only a single implementation of a strict 32-bit MIPS32r2 FPU (CP1.FIR.F64=0) has been ever made and that chip actually supports these instructions, and no future 32-bit FPUs are supposed to be made as the architecture no longer allows it[3][4]. Note that these instructions were allowed in either FPU mode in the MIPS IV ISA, but for forward ISA compatibility this change does not enable them for -march=mips4 in the 32-bit FPR mode because the original revision of the MIPS64 ISA did not support it. I have regression-tested this change with the mips-linux-gnu target and the mips32r2/o32 multilib. I have also verified that the instructions affected were absent across the binaries produced by the testsuite before applying this change and present afterwards -- although only RECIP.D and RECIP.S are produced and only once each, by gcc.dg/builtins-24.c and gcc.dg/pr41963.c respectively. Neither RSQRT.D nor RSQRT.S have coverage in our testsuite. OK to apply? References: [1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", Document Number: MD00086, Revision 5.03, Sept. 9, 2013 [2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 Instruction Set, Document Number: MD00582, Revision 5.03, Sept. 9, 2013 [3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the MIPS32 Architecture", Document Number: MD00082, Revision 5.03, Sept. 9, 2013 [4] "MIPSR Architecture For Programmers, Volume I-B: Introduction to the microMIPS32 Architecture", Document Number: MD00741, Revision 5.03, Sept. 9, 2013 2013-11-14 Maciej W. Rozycki gcc/ * config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro. * config/mips/mips.c (mips_rtx_costs)
: Check for ISA_HAS_FP_RECIP_RSQRT rather than ISA_HAS_FP4. * config/mips/mips.md (recip_condition): Remove mode attribute. (div3): Use ISA_HAS_FP_RECIP_RSQRT rather than . (*recip3, *rsqrta, *rsqrtb): Likewise. Maciej gcc-mips32r2-recip.patch Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.c =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.c 2013-11-12 15:32:19.767952530 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.c 2013-11-12 15:33:22.277646941 +0000 @@ -3967,7 +3967,7 @@ mips_rtx_costs (rtx x, int code, int out case DIV: /* Check for a reciprocal. */ if (float_mode_p - && ISA_HAS_FP4 + && ISA_HAS_FP_RECIP_RSQRT (mode) && flag_unsafe_math_optimizations && XEXP (x, 0) == CONST1_RTX (mode)) { Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.h =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.h 2013-11-12 15:31:46.758734464 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.h 2013-11-12 15:33:22.277646941 +0000 @@ -921,6 +921,21 @@ struct mips_cpu_info { 'c = -((a * b) [+-] c)'. */ #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF +/* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The + MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when + doubles are stored in pairs of FPRs, so for safety's sake, we apply + this restriction to the MIPS IV ISA too. */ +#define ISA_HAS_FP_RECIP_RSQRT(MODE) \ + (((ISA_HAS_FP4 \ + || (ISA_MIPS32R2 && !TARGET_MIPS16)) \ + && ((MODE) == SFmode \ + || ((TARGET_FLOAT64 \ + || !(ISA_MIPS4 \ + || ISA_MIPS64)) \ + && (MODE) == DFmode))) \ + || ((TARGET_SB1 && !TARGET_MIPS16) \ + && (MODE) == V2SFmode)) + /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ || ISA_MIPS32R2 \ Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.md =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.md 2013-11-12 15:31:46.758734464 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.md 2013-11-12 15:33:22.277646941 +0000 @@ -881,15 +881,6 @@ (define_mode_attr sqrt_condition [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) -;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt -;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D -;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs, -;; so for safety's sake, we apply this restriction to all targets. -(define_mode_attr recip_condition - [(SF "ISA_HAS_FP4") - (DF "ISA_HAS_FP4 && TARGET_FLOAT64") - (V2SF "TARGET_SB1")]) - ;; This code iterator allows signed and unsigned widening multiplications ;; to use the same template. (define_code_iterator any_extend [sign_extend zero_extend]) @@ -2501,7 +2492,8 @@ "" { if (const_1_operand (operands[1], mode)) - if (!( && flag_unsafe_math_optimizations)) + if (!(ISA_HAS_FP_RECIP_RSQRT (mode) + && flag_unsafe_math_optimizations)) operands[1] = force_reg (mode, operands[1]); }) @@ -2539,7 +2531,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") (match_operand:ANYF 2 "register_operand" "f")))] - " && flag_unsafe_math_optimizations" + "ISA_HAS_FP_RECIP_RSQRT (mode) && flag_unsafe_math_optimizations" { if (TARGET_FIX_SB1) return "recip.\t%0,%2\;mov.\t%0,%0"; @@ -2674,7 +2666,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] - " && flag_unsafe_math_optimizations" + "ISA_HAS_FP_RECIP_RSQRT (mode) && flag_unsafe_math_optimizations" { if (TARGET_FIX_SB1) return "rsqrt.\t%0,%2\;mov.\t%0,%0"; @@ -2692,7 +2684,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") (match_operand:ANYF 2 "register_operand" "f"))))] - " && flag_unsafe_math_optimizations" + "ISA_HAS_FP_RECIP_RSQRT (mode) && flag_unsafe_math_optimizations" { if (TARGET_FIX_SB1) return "rsqrt.\t%0,%2\;mov.\t%0,%0";