Patchwork [1/2] powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges

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Submitter Gavin Shan
Date Nov. 12, 2013, 6:49 a.m.
Message ID <1384238962-13170-1-git-send-email-shangw@linux.vnet.ibm.com>
Download mbox | patch
Permalink /patch/290542/
State Accepted
Commit bf898ec5cbd33be11147743bee27b66b10cb2f85
Headers show

Comments

Gavin Shan - Nov. 12, 2013, 6:49 a.m.
On PHB3, we will fail to fetch IODA tables without PCI_COMMAND_MASTER
on PCI bridges. According to one experiment I had, the MSIx interrupts
didn't raise from the adapter without the bit applied to all upstream
PCI bridges including root port of the adapter. The patch forces to
have that bit enabled accordingly.

Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/eeh.c |    9 +++++++++
 1 file changed, 9 insertions(+)

Patch

diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 1fb331d..180af13 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -687,6 +687,15 @@  void eeh_save_bars(struct eeh_dev *edev)
 
 	for (i = 0; i < 16; i++)
 		eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
+
+	/*
+	 * For PCI bridges including root port, we need enable bus
+	 * master explicitly. Otherwise, it can't fetch IODA table
+	 * entries correctly. So we cache the bit in advance so that
+	 * we can restore it after reset, either PHB range or PE range.
+	 */
+	if (edev->mode & EEH_DEV_BRIDGE)
+		edev->config_space[1] |= PCI_COMMAND_MASTER;
 }
 
 /**