From patchwork Fri Nov 8 21:17:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Albert ARIBAUD X-Patchwork-Id: 289919 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D30902C0040 for ; Sat, 9 Nov 2013 08:19:32 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 463624A472; Fri, 8 Nov 2013 22:19:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2TKTF8W6r9Qa; Fri, 8 Nov 2013 22:19:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 911B84A47E; Fri, 8 Nov 2013 22:19:04 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D43E24A460 for ; Fri, 8 Nov 2013 22:18:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q4zUimi2jw-8 for ; Fri, 8 Nov 2013 22:18:58 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp6-g21.free.fr (smtp6-g21.free.fr [212.27.42.6]) by theia.denx.de (Postfix) with ESMTP id 4728B4A45B for ; Fri, 8 Nov 2013 22:18:39 +0100 (CET) Received: from localhost.localdomain (unknown [IPv6:2a01:e35:2eb9:21:ae22:bff:fe1a:1040]) (Authenticated sender: aribaud.smtp) by smtp6-g21.free.fr (Postfix) with ESMTPSA id 6AA148225B; Fri, 8 Nov 2013 22:18:34 +0100 (CET) From: Albert ARIBAUD To: U-Boot Date: Fri, 8 Nov 2013 22:17:57 +0100 Message-Id: <1383945479-6499-5-git-send-email-albert.u.boot@aribaud.net> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1383945479-6499-4-git-send-email-albert.u.boot@aribaud.net> References: <1383945479-6499-1-git-send-email-albert.u.boot@aribaud.net> <1383945479-6499-2-git-send-email-albert.u.boot@aribaud.net> <1383945479-6499-3-git-send-email-albert.u.boot@aribaud.net> <1383945479-6499-4-git-send-email-albert.u.boot@aribaud.net> Subject: [U-Boot] [PATCH v1 4/6] arm: ixp: cosmetic: move code around in start.S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Make IPX start.S more consistant with other start.S files by moving defines and macros away so that the file begins with the exception vectors table. Signed-off-by: Albert ARIBAUD --- arch/arm/cpu/ixp/start.S | 64 ++++++++++++++++++++++++------------------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 0641593..9943e7f 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -16,38 +16,6 @@ #include #include -#define MMU_Control_M 0x001 /* Enable MMU */ -#define MMU_Control_A 0x002 /* Enable address alignment faults */ -#define MMU_Control_C 0x004 /* Enable cache */ -#define MMU_Control_W 0x008 /* Enable write-buffer */ -#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ -#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ -#define MMU_Control_L 0x040 /* Compatability: */ -#define MMU_Control_B 0x080 /* Enable Big-Endian */ -#define MMU_Control_S 0x100 /* Enable system protection */ -#define MMU_Control_R 0x200 /* Enable ROM protection */ -#define MMU_Control_I 0x1000 /* Enable Instruction cache */ -#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ -#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) - - -/* - * Macro definitions - */ - /* Delay a bit */ - .macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc - .endm - - /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - .globl _start _start: ldr pc, _reset @@ -101,6 +69,38 @@ IRQ_STACK_START_IN: * the actual reset code */ +#define MMU_Control_M 0x001 /* Enable MMU */ +#define MMU_Control_A 0x002 /* Enable address alignment faults */ +#define MMU_Control_C 0x004 /* Enable cache */ +#define MMU_Control_W 0x008 /* Enable write-buffer */ +#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ +#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ +#define MMU_Control_L 0x040 /* Compatability: */ +#define MMU_Control_B 0x080 /* Enable Big-Endian */ +#define MMU_Control_S 0x100 /* Enable system protection */ +#define MMU_Control_R 0x200 /* Enable ROM protection */ +#define MMU_Control_I 0x1000 /* Enable Instruction cache */ +#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ +#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) + + +/* + * Macro definitions + */ + /* Delay a bit */ + .macro DELAY_FOR cycles, reg0 + ldr \reg0, =\cycles + subs \reg0, \reg0, #1 + subne pc, pc, #0xc + .endm + + /* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + reset: /* disable mmu, set big-endian */ mov r0, #0xf8