Patchwork [U-Boot,v1,4/6] arm: ixp: cosmetic: move code around in start.S

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Submitter Albert ARIBAUD
Date Nov. 8, 2013, 9:17 p.m.
Message ID <1383945479-6499-5-git-send-email-albert.u.boot@aribaud.net>
Download mbox | patch
Permalink /patch/289919/
State Not Applicable
Delegated to: Albert ARIBAUD
Headers show

Comments

Albert ARIBAUD - Nov. 8, 2013, 9:17 p.m.
Make IPX start.S more consistant with other start.S files
by moving defines and macros away so that the file begins
with the exception vectors table.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 arch/arm/cpu/ixp/start.S | 64 ++++++++++++++++++++++++------------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

Patch

diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
index 0641593..9943e7f 100644
--- a/arch/arm/cpu/ixp/start.S
+++ b/arch/arm/cpu/ixp/start.S
@@ -16,38 +16,6 @@ 
 #include <version.h>
 #include <asm/arch/ixp425.h>
 
-#define MMU_Control_M  0x001    /* Enable MMU */
-#define MMU_Control_A  0x002    /* Enable address alignment faults */
-#define MMU_Control_C  0x004    /* Enable cache */
-#define MMU_Control_W  0x008    /* Enable write-buffer */
-#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
-#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
-#define MMU_Control_L  0x040    /* Compatability: */
-#define MMU_Control_B  0x080    /* Enable Big-Endian */
-#define MMU_Control_S  0x100    /* Enable system protection */
-#define MMU_Control_R  0x200    /* Enable ROM protection */
-#define MMU_Control_I  0x1000   /* Enable Instruction cache */
-#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
-	/* Delay a bit */
-	.macro DELAY_FOR cycles, reg0
-	ldr     \reg0, =\cycles
-	subs    \reg0, \reg0, #1
-	subne   pc,  pc, #0xc
-	.endm
-
-	/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
 .globl _start
 _start:
 	ldr	pc, _reset
@@ -101,6 +69,38 @@  IRQ_STACK_START_IN:
  * the actual reset code
  */
 
+#define MMU_Control_M  0x001    /* Enable MMU */
+#define MMU_Control_A  0x002    /* Enable address alignment faults */
+#define MMU_Control_C  0x004    /* Enable cache */
+#define MMU_Control_W  0x008    /* Enable write-buffer */
+#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
+#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
+#define MMU_Control_L  0x040    /* Compatability: */
+#define MMU_Control_B  0x080    /* Enable Big-Endian */
+#define MMU_Control_S  0x100    /* Enable system protection */
+#define MMU_Control_R  0x200    /* Enable ROM protection */
+#define MMU_Control_I  0x1000   /* Enable Instruction cache */
+#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
+#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
+
+
+/*
+ * Macro definitions
+ */
+	/* Delay a bit */
+	.macro DELAY_FOR cycles, reg0
+	ldr     \reg0, =\cycles
+	subs    \reg0, \reg0, #1
+	subne   pc,  pc, #0xc
+	.endm
+
+	/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
+	sub  pc,pc,#4
+	.endm
+
 reset:
 	/* disable mmu, set big-endian */
 	mov	r0, #0xf8