From patchwork Fri Nov 8 17:41:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steven Bosscher X-Patchwork-Id: 289898 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 659882C007E for ; Sat, 9 Nov 2013 04:50:55 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=GHXHGKnWKdNpu5R Okw6MLbSsEaNaV8zV2n+PZYR4GWWmHzw9b44CJ9LSfarxiaJlYwPXJBqR/kVWABJ C/ZlJL/b3kbs8YTfqSwLDsrPxQAT7rOEMArpLm0IU7/k5JuOxY/n6INf4y2WoEe0 WE2zKZOPnJbTjXJD2whl2+kA06Kw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; s=default; bh=kJudMg92HX9ZtES1/lqpu i54dVI=; b=xrYOXjB7x+Gopv/vfVRNPNY/lf5nplKZO0KNuf7TEmktc77lbv4nS 9b6uQABkowK252etSAEs5BSJuYV5HQGEcCzGPuILVu+c8HuYyPoWFvBb+UBVVCSr dYMkdtbv4S25ghBKi8HxE07TIkbXot+pSV4QiNqVAPn51sf8tqMbNg= Received: (qmail 3925 invoked by alias); 8 Nov 2013 17:50:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 417 invoked by uid 89); 8 Nov 2013 17:42:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.6 required=5.0 tests=AWL, BAYES_50, FREEMAIL_FROM, RDNS_NONE, SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-ob0-f176.google.com Received: from Unknown (HELO mail-ob0-f176.google.com) (209.85.214.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 08 Nov 2013 17:42:34 +0000 Received: by mail-ob0-f176.google.com with SMTP id wp4so516313obc.35 for ; Fri, 08 Nov 2013 09:42:26 -0800 (PST) X-Received: by 10.60.40.136 with SMTP id x8mr5646818oek.49.1383932545655; Fri, 08 Nov 2013 09:42:25 -0800 (PST) MIME-Version: 1.0 Received: by 10.182.24.201 with HTTP; Fri, 8 Nov 2013 09:41:44 -0800 (PST) In-Reply-To: References: <52601731.3000301@redhat.com> From: Steven Bosscher Date: Fri, 8 Nov 2013 18:41:44 +0100 Message-ID: Subject: Re: [PATCH] Enhance ifcombine to recover non short circuit branches To: Andrew Pinski Cc: Richard Biener , Zhenqiang Chen , Jeff Law , "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes On Fri, Nov 8, 2013 at 6:20 PM, Steven Bosscher wrote: > On Wed, Oct 30, 2013 at 5:03 AM, Andrew Pinski wrote: >> Here is what I applied in the end; Jeff told me just to remove the >> testcase. I added the comment trying to explain why it was the >> opposite order of PHI-opt. >> >> Thanks, >> Andrew Pinski >> >> ChangeLog: >> * tree-ssa-ifcombine.c: Include rtl.h and tm_p.h. > > Eh, why??? > > The file has this comment: > > 25 /* rtl is needed only because arm back-end requires it for > 26 BRANCH_COST. */ > 27 #include "rtl.h" > 28 #include "tm_p.h" > > Can you please clarify why this is not something to be fixed in the > ARM back end? Could be fixed like attached. Can you please have a look and foster-parent it if you like it? Thanks, Ciao! Steven * config/arm/arm-protos.h (arm_branch_cost, arm_logical_op_non_short_circuit): New prototypes. * config/arm/arm.c (arm_branch_cost): Implement it. (arm_logical_op_non_short_circuit): Likewise. * config/arm/arm.h (BRANCH_COST): Don't expose ARM back-end internals to the RTL middle end. (LOGICAL_OP_NON_SHORT_CIRCUIT): Likewise. * tree-ssa-ifcombine.c: Don't include rtl.h here. * tree-ssa-reassoc.c: Don't include rtl.h here either. Index: config/arm/arm-protos.h =================================================================== --- config/arm/arm-protos.h (revision 204565) +++ config/arm/arm-protos.h (working copy) @@ -288,4 +288,7 @@ extern bool arm_autoinc_modes_ok_p (enum machine_m extern void arm_emit_eabi_attribute (const char *, int, int); +extern bool arm_branch_cost (bool, bool); +extern bool arm_logical_op_non_short_circuit (void); + #endif /* ! GCC_ARM_PROTOS_H */ Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 204565) +++ config/arm/arm.c (working copy) @@ -30351,4 +30351,19 @@ arm_asan_shadow_offset (void) return (unsigned HOST_WIDE_INT) 1 << 29; } +/* Implement BRANCH_COST as a function, to hide tune_params from the + rest of the compiler. */ +bool +arm_branch_cost (bool speed_p, bool predictable_p) +{ + return current_tune->branch_cost (speed_p, predictable_p); +} + +/* Likewise for LOGICAL_OP_NON_SHORT_CIRCUIT. */ +bool +arm_logical_op_non_short_circuit (void) +{ + return (current_tune->logical_op_non_short_circuit[TARGET_ARM]); +} + #include "gt-arm.h" Index: config/arm/arm.h =================================================================== --- config/arm/arm.h (revision 204565) +++ config/arm/arm.h (working copy) @@ -2042,14 +2042,13 @@ enum arm_auto_incmodes /* Try to generate sequences that don't involve branches, we can then use conditional instructions. */ #define BRANCH_COST(speed_p, predictable_p) \ - (current_tune->branch_cost (speed_p, predictable_p)) + arm_branch_cost (speed_p, predictable_p) /* False if short circuit operation is preferred. */ #define LOGICAL_OP_NON_SHORT_CIRCUIT \ ((optimize_size) \ ? (TARGET_THUMB ? false : true) \ - : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) - + : arm_logical_op_non_short_circuit () /* Position Independent Code. */ /* We decide which register to use based on the compilation options and Index: tree-ssa-ifcombine.c =================================================================== --- tree-ssa-ifcombine.c (revision 204565) +++ tree-ssa-ifcombine.c (working copy) @@ -22,9 +22,6 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tm.h" -/* rtl is needed only because arm back-end requires it for - BRANCH_COST. */ -#include "rtl.h" #include "tm_p.h" #include "tree.h" #include "basic-block.h" Index: tree-ssa-reassoc.c =================================================================== --- tree-ssa-reassoc.c (revision 204565) +++ tree-ssa-reassoc.c (working copy) @@ -23,7 +23,6 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "hash-table.h" #include "tm.h" -#include "rtl.h" #include "tm_p.h" #include "tree.h" #include "basic-block.h"