Patchwork ARM: i.MX5x: Add SAHARA clock for i.MX5x CPUs

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Submitter Alexander Shiyan
Date Nov. 8, 2013, 9 a.m.
Message ID <1383901222-12013-1-git-send-email-shc_work@mail.ru>
Download mbox | patch
Permalink /patch/289721/
State New
Headers show

Comments

Alexander Shiyan - Nov. 8, 2013, 9 a.m.
Patch adds missing Security Accelerator (SAHARA) clock for i.MX5x CPUs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 +
 arch/arm/mach-imx/clk-imx51-imx53.c                    | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)
Shawn Guo - Nov. 11, 2013, 7:07 a.m.
On Fri, Nov 08, 2013 at 01:00:22PM +0400, Alexander Shiyan wrote:
> Patch adds missing Security Accelerator (SAHARA) clock for i.MX5x CPUs.
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>

Applied, thanks.

Patch

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 4c029a8..a8bbe77 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -198,6 +198,7 @@  clocks and IDs.
 	spdif1_gate		184
 	spdif_ipg_gate		185
 	ocram			186
+	sahara_ipg_gate		187
 
 Examples (for mx53):
 
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 219c65e..931f7f9 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -123,7 +123,7 @@  enum imx5_clks {
 	srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
 	spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
 	spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
-	ocram, clk_max
+	ocram, sahara_ipg_gate, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -286,6 +286,7 @@  static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 				spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
 	clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
 	clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
+	clk[sahara_ipg_gate] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
 
 	for (i = 0; i < ARRAY_SIZE(clk); i++)
 		if (IS_ERR(clk[i]))