From patchwork Thu Nov 7 13:36:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Zijlstra X-Patchwork-Id: 289334 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id BA07C2C0196 for ; Fri, 8 Nov 2013 00:37:29 +1100 (EST) Received: by ozlabs.org (Postfix) id 681D02C00DE; Fri, 8 Nov 2013 00:37:03 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 25F062C00D1 for ; Fri, 8 Nov 2013 00:37:03 +1100 (EST) Received: from dhcp-077-248-225-117.chello.nl ([77.248.225.117] helo=twins) by merlin.infradead.org with esmtpsa (Exim 4.80.1 #2 (Red Hat Linux)) id 1VePlF-0007LA-C0; Thu, 07 Nov 2013 13:36:37 +0000 Received: by twins (Postfix, from userid 1000) id 61D2C83B0E82; Thu, 7 Nov 2013 14:36:25 +0100 (CET) Date: Thu, 7 Nov 2013 14:36:25 +0100 From: Peter Zijlstra To: Will Deacon Subject: Re: [RFC] arch: Introduce new TSO memory barrier smp_tmb() Message-ID: <20131107133625.GU10651@twins.programming.kicks-ass.net> References: <20131104105059.GL3947@linux.vnet.ibm.com> <20131104112254.GK28601@twins.programming.kicks-ass.net> <20131104162732.GN3947@linux.vnet.ibm.com> <20131104191127.GW16117@laptop.programming.kicks-ass.net> <20131104205344.GW3947@linux.vnet.ibm.com> <20131106123946.GJ10651@twins.programming.kicks-ass.net> <20131106135736.GK10651@twins.programming.kicks-ass.net> <20131107111741.GD13139@mudshark.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20131107111741.GD13139@mudshark.cambridge.arm.com> User-Agent: Mutt/1.5.21 (2012-12-30) Cc: Michael Neuling , Tony Luck , Mathieu Desnoyers , Heiko Carstens , Oleg Nesterov , LKML , Linux PPC dev , Geert Uytterhoeven , Anton Blanchard , Frederic Weisbecker , Victor Kaplansky , Russell King , "Paul E. McKenney" , Linus Torvalds , Martin Schwidefsky X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16rc2 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Nov 07, 2013 at 11:17:41AM +0000, Will Deacon wrote: > Hi Peter, > > Couple of minor fixes on the arm64 side... > > On Wed, Nov 06, 2013 at 01:57:36PM +0000, Peter Zijlstra wrote: > > --- a/arch/arm64/include/asm/barrier.h > > +++ b/arch/arm64/include/asm/barrier.h > > @@ -35,11 +35,59 @@ > > #define smp_mb() barrier() > > #define smp_rmb() barrier() > > #define smp_wmb() barrier() > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + compiletime_assert_atomic_type(*p); \ > > + smp_mb(); \ > > + ACCESS_ONCE(*p) = (v); \ > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +({ \ > > + typeof(*p) ___p1 = ACCESS_ONCE(*p); \ > > + compiletime_assert_atomic_type(*p); \ > > + smp_mb(); \ > > + ___p1; \ > > +}) > > + > > #else > > + > > #define smp_mb() asm volatile("dmb ish" : : : "memory") > > #define smp_rmb() asm volatile("dmb ishld" : : : "memory") > > #define smp_wmb() asm volatile("dmb ishst" : : : "memory") > > -#endif > > Why are you getting rid of this #endif? oops.. > > +#define smp_store_release(p, v) \ > > +do { \ > > + compiletime_assert_atomic_type(*p); \ > > + switch (sizeof(*p)) { \ > > + case 4: \ > > + asm volatile ("stlr %w1, [%0]" \ > > + : "=Q" (*p) : "r" (v) : "memory"); \ > > + break; \ > > + case 8: \ > > + asm volatile ("stlr %1, [%0]" \ > > + : "=Q" (*p) : "r" (v) : "memory"); \ > > + break; \ > > + } \ > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +({ \ > > + typeof(*p) ___p1; \ > > + compiletime_assert_atomic_type(*p); \ > > + switch (sizeof(*p)) { \ > > + case 4: \ > > + asm volatile ("ldar %w0, [%1]" \ > > + : "=r" (___p1) : "Q" (*p) : "memory"); \ > > + break; \ > > + case 8: \ > > + asm volatile ("ldar %0, [%1]" \ > > + : "=r" (___p1) : "Q" (*p) : "memory"); \ > > + break; \ > > + } \ > > + ___p1; \ > > +}) > > You don't need the square brackets when using the "Q" constraint (otherwise > it will expand to something like [[x0]], which gas won't accept). > > With those changes, for the general idea and arm/arm64 parts: > > Acked-by: Will Deacon Thanks, I did that split-up I talked about yesterday, I was going to compile them for all archs I have a compiler for before posting again. --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -62,11 +62,11 @@ do { \ compiletime_assert_atomic_type(*p); \ switch (sizeof(*p)) { \ case 4: \ - asm volatile ("stlr %w1, [%0]" \ + asm volatile ("stlr %w1, %0" \ : "=Q" (*p) : "r" (v) : "memory"); \ break; \ case 8: \ - asm volatile ("stlr %1, [%0]" \ + asm volatile ("stlr %1, %0" \ : "=Q" (*p) : "r" (v) : "memory"); \ break; \ } \ @@ -78,17 +78,19 @@ do { \ compiletime_assert_atomic_type(*p); \ switch (sizeof(*p)) { \ case 4: \ - asm volatile ("ldar %w0, [%1]" \ + asm volatile ("ldar %w0, %1" \ : "=r" (___p1) : "Q" (*p) : "memory"); \ break; \ case 8: \ - asm volatile ("ldar %0, [%1]" \ + asm volatile ("ldar %0, %1" \ : "=r" (___p1) : "Q" (*p) : "memory"); \ break; \ } \ ___p1; \ }) +#endif + #define read_barrier_depends() do { } while(0) #define smp_read_barrier_depends() do { } while(0)