From patchwork Thu Nov 7 01:05:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 289183 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 32D472C00AD for ; Thu, 7 Nov 2013 15:27:13 +1100 (EST) Received: from localhost ([::1]:36990 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeEGf-0000H0-1x for incoming@patchwork.ozlabs.org; Wed, 06 Nov 2013 20:20:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE4w-0000KM-6X for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE4q-0006UF-BH for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:10 -0500 Received: from mail-pd0-x230.google.com ([2607:f8b0:400e:c02::230]:36433) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE4p-0006Tw-WA for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:04 -0500 Received: by mail-pd0-f176.google.com with SMTP id g10so306506pdj.7 for ; Wed, 06 Nov 2013 17:08:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=9xoWtQfyvvlL529jKpdN4D2nwOyTC7i1Nx62cvwDy2c=; b=yS4azvHMNvhylahfYYZRGbH3PNqLQQD6JDJogmSGxQtsGNW4yx2DXgOe4QdbrsJB22 KhAbjlDO1FDe2aPJWZNWKJ7RYQMgNVIDsAuxXPw3ncnhSvuAQQMI5qj/FMeXOzE92WQM Xnxf+71XN8z1ysRGjNdobahwyrWp9Zak7zp70nTGPhb8cqptXXenytYoa9bBgJl9lh77 iHJ+OHSswOLlRzwUakU3lX7Zw1I6lz3ph30kkm/h5+Xr+lNIyIjhsfuCT5q6vo8htuhy 85EH3yHeWuJUOf+NanGNUgKcLBsBWD7E1sft4kVoAtJHI/thChM7+zA54FGyZFT2Lfdw Yvzg== X-Received: by 10.67.14.67 with SMTP id fe3mr6888550pad.134.1383786483007; Wed, 06 Nov 2013 17:08:03 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.08.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:08:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:05:09 +1000 Message-Id: <1383786324-18415-47-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::230 Subject: [Qemu-devel] [PATCH for-1.8 46/61] target-i386: Access segs via TCG registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Having segs[].base as a register significantly improves code generation for real and protected modes, particularly for TBs that have multiple memory references where the segment base can be held in a hard register through the TB. Signed-off-by: Richard Henderson --- target-i386/translate.c | 71 ++++++++++++++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 73ff589..3bb77eb 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -65,6 +65,8 @@ static TCGv cpu_A0; static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT; static TCGv_i32 cpu_cc_op; static TCGv cpu_regs[CPU_NB_REGS]; +static TCGv_i32 cpu_seg_sel[6]; +static TCGv cpu_seg_base[6]; /* local temps */ static TCGv cpu_T[2]; /* local register indexes (only used inside old micro ops) */ @@ -442,12 +444,11 @@ static inline void gen_op_add_reg_T0(TCGMemOp size, int reg) static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) { - tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); if (CODE64(s)) { tcg_gen_ext32u_tl(cpu_A0, cpu_A0); - tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); + tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_seg_base[reg]); } else { - tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); + tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_seg_base[reg]); tcg_gen_ext32u_tl(cpu_A0, cpu_A0); } } @@ -519,9 +520,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0, } if (ovr_seg >= 0) { - TCGv seg = tcg_temp_new(); - - tcg_gen_ld_tl(seg, cpu_env, offsetof(CPUX86State, segs[ovr_seg].base)); + TCGv seg = cpu_seg_base[ovr_seg]; if (aflag == MO_64) { tcg_gen_add_tl(cpu_A0, a0, seg); @@ -532,8 +531,6 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0, tcg_gen_add_tl(cpu_A0, a0, seg); tcg_gen_ext32u_tl(cpu_A0, cpu_A0); } - - tcg_temp_free(seg); } } @@ -2218,18 +2215,14 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b, static inline void gen_op_movl_T0_seg(int seg_reg) { - tcg_gen_ld32u_tl(cpu_T[0], cpu_env, - offsetof(CPUX86State,segs[seg_reg].selector)); + tcg_gen_extu_i32_tl(cpu_T[0], cpu_seg_sel[seg_reg]); } static inline void gen_op_movl_seg_T0_vm(int seg_reg) { - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); - tcg_gen_st32_tl(cpu_T[0], cpu_env, - offsetof(CPUX86State,segs[seg_reg].selector)); - tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); - tcg_gen_st_tl(cpu_T[0], cpu_env, - offsetof(CPUX86State,segs[seg_reg].base)); + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_trunc_tl_i32(cpu_seg_sel[seg_reg], cpu_T[0]); + tcg_gen_shli_tl(cpu_seg_base[seg_reg], cpu_T[0], 4); } /* move T0 to seg_reg and compute if the CPU state may change. Never @@ -7296,21 +7289,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - tcg_gen_ld_tl(cpu_T[0], cpu_env, - offsetof(CPUX86State,segs[R_GS].base)); - tcg_gen_ld_tl(cpu_T[1], cpu_env, - offsetof(CPUX86State,kernelgsbase)); - tcg_gen_st_tl(cpu_T[1], cpu_env, - offsetof(CPUX86State,segs[R_GS].base)); + tcg_gen_mov_tl(cpu_T[0], cpu_seg_base[R_GS]); + tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env, + offsetof(CPUX86State, kernelgsbase)); tcg_gen_st_tl(cpu_T[0], cpu_env, - offsetof(CPUX86State,kernelgsbase)); + offsetof(CPUX86State, kernelgsbase)); } - } else -#endif - { - goto illegal_op; + break; } - break; +#endif + goto illegal_op; case 1: /* rdtscp */ if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) goto illegal_op; @@ -7736,6 +7724,22 @@ void optimize_flags_init(void) [R_ESP] = "esp", #endif }; + static const char seg_base_names[6][8] = { + [R_CS] = "cs_base", + [R_DS] = "ds_base", + [R_ES] = "es_base", + [R_FS] = "fs_base", + [R_GS] = "gs_base", + [R_SS] = "ss_base", + }; + static const char seg_sel_names[6][8] = { + [R_CS] = "cs_sel", + [R_DS] = "ds_sel", + [R_ES] = "es_sel", + [R_FS] = "fs_sel", + [R_GS] = "gs_sel", + [R_SS] = "ss_sel", + }; int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); @@ -7753,6 +7757,17 @@ void optimize_flags_init(void) offsetof(CPUX86State, regs[i]), reg_names[i]); } + + for (i = 0; i < 6; ++i) { + cpu_seg_base[i] + = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUX86State, segs[i].base), + seg_base_names[i]); + cpu_seg_sel[i] + = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUX86State, segs[i].selector), + seg_sel_names[i]); + } } /* generate intermediate code in gen_opc_buf and gen_opparam_buf for