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[138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.07.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:04:59 +1000 Message-Id: <1383786324-18415-37-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22d Subject: [Qemu-devel] [PATCH for-1.8 36/61] target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Change the domain of the parameter and update all callers. Which lets us defer completely to gen_op_mov_reg_v. Signed-off-by: Richard Henderson --- target-i386/translate.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 747eefd..a966d8f 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -334,25 +334,9 @@ static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg) gen_op_mov_reg_v(ot, reg, cpu_T[1]); } -static void gen_op_mov_reg_A0(TCGMemOp size, int reg) +static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg) { - switch (size) { - case MO_8: - tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); - break; - case MO_16: - /* For x86_64, this sets the higher half of register to zero. - For i386, this is equivalent to a mov. */ - tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); - break; -#ifdef TARGET_X86_64 - case MO_32: - tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); - break; -#endif - default: - tcg_abort(); - } + gen_op_mov_reg_v(size, reg, cpu_A0); } static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg) @@ -2373,7 +2357,7 @@ static void gen_push_T0(DisasContext *s) gen_op_addq_A0_im(-2); gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); } - gen_op_mov_reg_A0(2, R_ESP); + gen_op_mov_reg_A0(MO_64, R_ESP); } else #endif { @@ -2394,9 +2378,9 @@ static void gen_push_T0(DisasContext *s) } gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0); if (s->ss32 && !s->addseg) - gen_op_mov_reg_A0(1, R_ESP); + gen_op_mov_reg_A0(MO_32, R_ESP); else - gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); + gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); } } @@ -2414,7 +2398,7 @@ static void gen_push_T1(DisasContext *s) gen_op_addq_A0_im(-2); gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); } - gen_op_mov_reg_A0(2, R_ESP); + gen_op_mov_reg_A0(MO_64, R_ESP); } else #endif { @@ -2434,7 +2418,7 @@ static void gen_push_T1(DisasContext *s) gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); if (s->ss32 && !s->addseg) - gen_op_mov_reg_A0(1, R_ESP); + gen_op_mov_reg_A0(MO_32, R_ESP); else gen_stack_update(s, (-2) << s->dflag); } @@ -5558,7 +5542,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, s->addseg = 0; gen_lea_modrm(env, s, modrm); s->addseg = val; - gen_op_mov_reg_A0(ot - MO_16, reg); + gen_op_mov_reg_A0(ot, reg); break; case 0xa0: /* mov EAX, Ov */