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[138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.08.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:08:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:05:17 +1000 Message-Id: <1383786324-18415-55-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22e Subject: [Qemu-devel] [PATCH for-1.8 54/61] target-i386: Remove gen_op_mov_TN_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Replace with its definition, via Coccinelle. Signed-off-by: Richard Henderson --- target-i386/translate.c | 111 +++++++++++++++++++++++------------------------- 1 file changed, 53 insertions(+), 58 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index cae0cb5..5dd68e1 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -381,11 +381,6 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg) } } -static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg) -{ - gen_op_mov_v_reg(ot, cpu_T[t_index], reg); -} - static inline void gen_op_movl_A0_reg(int reg) { tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); @@ -1088,7 +1083,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) static inline void gen_stos(DisasContext *s, TCGMemOp ot) { - gen_op_mov_TN_reg(MO_32, 0, R_EAX); + gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX); gen_string_movl_A0_EDI(s); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_movl_T0_Dshift(ot); @@ -1265,7 +1260,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg) static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) { if (d != OR_TMP0) { - gen_op_mov_TN_reg(ot, 0, d); + gen_op_mov_v_reg(ot, cpu_T[0], d); } else { gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0); } @@ -1331,7 +1326,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) { if (d != OR_TMP0) { - gen_op_mov_TN_reg(ot, 0, d); + gen_op_mov_v_reg(ot, cpu_T[0], d); } else { gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0); } @@ -1401,7 +1396,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1, if (op1 == OR_TMP0) { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, op1); + gen_op_mov_v_reg(ot, cpu_T[0], op1); } tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); @@ -1437,7 +1432,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, if (op1 == OR_TMP0) gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); else - gen_op_mov_TN_reg(ot, 0, op1); + gen_op_mov_v_reg(ot, cpu_T[0], op1); op2 &= mask; if (op2 != 0) { @@ -1485,7 +1480,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right) if (op1 == OR_TMP0) { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, op1); + gen_op_mov_v_reg(ot, cpu_T[0], op1); } tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); @@ -1571,7 +1566,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, if (op1 == OR_TMP0) { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, op1); + gen_op_mov_v_reg(ot, cpu_T[0], op1); } op2 &= mask; @@ -1649,7 +1644,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1, if (op1 == OR_TMP0) gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); else - gen_op_mov_TN_reg(ot, 0, op1); + gen_op_mov_v_reg(ot, cpu_T[0], op1); if (is_right) { switch (ot) { @@ -1705,7 +1700,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, if (op1 == OR_TMP0) { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, op1); + gen_op_mov_v_reg(ot, cpu_T[0], op1); } count = tcg_temp_new(); @@ -1779,7 +1774,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s) { if (s != OR_TMP1) - gen_op_mov_TN_reg(ot, 1, s); + gen_op_mov_v_reg(ot, cpu_T[1], s); switch(op) { case OP_ROL: gen_rot_rm_T1(s1, ot, d, 0); @@ -2059,10 +2054,10 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, if (mod == 3) { if (is_store) { if (reg != OR_TMP0) - gen_op_mov_TN_reg(ot, 0, reg); + gen_op_mov_v_reg(ot, cpu_T[0], reg); gen_op_mov_reg_v(ot, rm, cpu_T[0]); } else { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); if (reg != OR_TMP0) gen_op_mov_reg_v(ot, reg, cpu_T[0]); } @@ -2070,7 +2065,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, gen_lea_modrm(env, s, modrm); if (is_store) { if (reg != OR_TMP0) - gen_op_mov_TN_reg(ot, 0, reg); + gen_op_mov_v_reg(ot, cpu_T[0], reg); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } else { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); @@ -4010,7 +4005,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, break; case 0x20: /* pinsrb */ if (mod == 3) { - gen_op_mov_TN_reg(MO_32, 0, rm); + gen_op_mov_v_reg(MO_32, cpu_T[0], rm); } else { tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, s->mem_index, MO_UB); @@ -4465,7 +4460,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { opreg = rm; } - gen_op_mov_TN_reg(ot, 1, reg); + gen_op_mov_v_reg(ot, cpu_T[1], reg); gen_op(s, op, ot, opreg); break; case 1: /* OP Gv, Ev */ @@ -4479,7 +4474,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else if (op == OP_XORL && rm == reg) { goto xor_zero; } else { - gen_op_mov_TN_reg(ot, 1, rm); + gen_op_mov_v_reg(ot, cpu_T[1], rm); } gen_op(s, op, ot, reg); break; @@ -4559,7 +4554,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); } switch(op) { @@ -4590,7 +4585,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 4: /* mul */ switch(ot) { case MO_8: - gen_op_mov_TN_reg(MO_8, 1, R_EAX); + gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX); tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); /* XXX: use 32 bit mul which could be faster */ @@ -4601,7 +4596,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, set_cc_op(s, CC_OP_MULB); break; case MO_16: - gen_op_mov_TN_reg(MO_16, 1, R_EAX); + gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX); tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); /* XXX: use 32 bit mul which could be faster */ @@ -4639,7 +4634,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 5: /* imul */ switch(ot) { case MO_8: - gen_op_mov_TN_reg(MO_8, 1, R_EAX); + gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX); tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); /* XXX: use 32 bit mul which could be faster */ @@ -4651,7 +4646,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, set_cc_op(s, CC_OP_MULB); break; case MO_16: - gen_op_mov_TN_reg(MO_16, 1, R_EAX); + gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX); tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); /* XXX: use 32 bit mul which could be faster */ @@ -4768,7 +4763,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (op >= 2 && op != 3 && op != 5) gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); } switch(op) { @@ -4858,7 +4853,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = ((modrm >> 3) & 7) | rex_r; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - gen_op_mov_TN_reg(ot, 1, reg); + gen_op_mov_v_reg(ot, cpu_T[1], reg); gen_op_testl_T0_T1_cc(); set_cc_op(s, CC_OP_LOGICB + ot); break; @@ -4868,7 +4863,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = mo_b_d(b, dflag); val = insn_get(env, s, ot); - gen_op_mov_TN_reg(ot, 0, OR_EAX); + gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX); tcg_gen_movi_tl(cpu_T[1], val); gen_op_testl_T0_T1_cc(); set_cc_op(s, CC_OP_LOGICB + ot); @@ -4878,18 +4873,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch (dflag) { #ifdef TARGET_X86_64 case MO_64: - gen_op_mov_TN_reg(MO_32, 0, R_EAX); + gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX); tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]); break; #endif case MO_32: - gen_op_mov_TN_reg(MO_16, 0, R_EAX); + gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX); tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]); break; case MO_16: - gen_op_mov_TN_reg(MO_8, 0, R_EAX); + gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX); tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]); break; @@ -4901,19 +4896,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch (dflag) { #ifdef TARGET_X86_64 case MO_64: - gen_op_mov_TN_reg(MO_64, 0, R_EAX); + gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX); tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]); break; #endif case MO_32: - gen_op_mov_TN_reg(MO_32, 0, R_EAX); + gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX); tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]); break; case MO_16: - gen_op_mov_TN_reg(MO_16, 0, R_EAX); + gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX); tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]); @@ -4940,7 +4935,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = (int8_t)insn_get(env, s, MO_8); tcg_gen_movi_tl(cpu_T[1], val); } else { - gen_op_mov_TN_reg(ot, 1, reg); + gen_op_mov_v_reg(ot, cpu_T[1], reg); } switch (ot) { #ifdef TARGET_X86_64 @@ -4983,14 +4978,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, mod = (modrm >> 6) & 3; if (mod == 3) { rm = (modrm & 7) | REX_B(s); - gen_op_mov_TN_reg(ot, 0, reg); - gen_op_mov_TN_reg(ot, 1, rm); + gen_op_mov_v_reg(ot, cpu_T[0], reg); + gen_op_mov_v_reg(ot, cpu_T[1], rm); tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_mov_reg_v(ot, reg, cpu_T[1]); gen_op_mov_reg_v(ot, rm, cpu_T[0]); } else { gen_lea_modrm(env, s, modrm); - gen_op_mov_TN_reg(ot, 0, reg); + gen_op_mov_v_reg(ot, cpu_T[0], reg); gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); @@ -5084,7 +5079,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* push/pop */ case 0x50 ... 0x57: /* push */ - gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s)); + gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s)); gen_push_v(s, cpu_T[0]); break; case 0x58 ... 0x5f: /* pop */ @@ -5278,7 +5273,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); if (mod == 3) { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); switch (s_ot) { case MO_UB: tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); @@ -5344,7 +5339,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]); } else { - gen_op_mov_TN_reg(ot, 0, R_EAX); + gen_op_mov_v_reg(ot, cpu_T[0], R_EAX); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } } @@ -5399,13 +5394,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod == 3) { rm = (modrm & 7) | REX_B(s); do_xchg_reg: - gen_op_mov_TN_reg(ot, 0, reg); - gen_op_mov_TN_reg(ot, 1, rm); + gen_op_mov_v_reg(ot, cpu_T[0], reg); + gen_op_mov_v_reg(ot, cpu_T[1], rm); gen_op_mov_reg_v(ot, rm, cpu_T[0]); gen_op_mov_reg_v(ot, reg, cpu_T[1]); } else { gen_lea_modrm(env, s, modrm); - gen_op_mov_TN_reg(ot, 0, reg); + gen_op_mov_v_reg(ot, cpu_T[0], reg); /* for xchg, lock is implicit */ if (!(prefixes & PREFIX_LOCK)) gen_helper_lock(); @@ -5525,7 +5520,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { opreg = rm; } - gen_op_mov_TN_reg(ot, 1, reg); + gen_op_mov_v_reg(ot, cpu_T[1], reg); if (shift) { TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++)); @@ -6166,7 +6161,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = cpu_ldub_code(env, s->pc++); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); - gen_op_mov_TN_reg(ot, 1, R_EAX); + gen_op_mov_v_reg(ot, cpu_T[1], R_EAX); if (use_icount) gen_io_start(); @@ -6200,7 +6195,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); - gen_op_mov_TN_reg(ot, 1, R_EAX); + gen_op_mov_v_reg(ot, cpu_T[1], R_EAX); if (use_icount) gen_io_start(); @@ -6456,7 +6451,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x9e: /* sahf */ if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) goto illegal_op; - gen_op_mov_TN_reg(MO_8, 0, R_AH); + gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH); gen_compute_eflags(s); tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); @@ -6504,7 +6499,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); } /* load shift */ val = cpu_ldub_code(env, s->pc++); @@ -6530,7 +6525,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); - gen_op_mov_TN_reg(MO_32, 1, reg); + gen_op_mov_v_reg(MO_32, cpu_T[1], reg); if (mod != 3) { gen_lea_modrm(env, s, modrm); /* specific case: we need to add a displacement */ @@ -6540,7 +6535,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); } bt_op: tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); @@ -6785,7 +6780,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - gen_op_mov_TN_reg(ot, 0, reg); + gen_op_mov_v_reg(ot, cpu_T[0], reg); gen_lea_modrm(env, s, modrm); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); @@ -6799,13 +6794,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = (b & 7) | REX_B(s); #ifdef TARGET_X86_64 if (dflag == MO_64) { - gen_op_mov_TN_reg(MO_64, 0, reg); + gen_op_mov_v_reg(MO_64, cpu_T[0], reg); tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); gen_op_mov_reg_v(MO_64, reg, cpu_T[0]); } else #endif { - gen_op_mov_TN_reg(MO_32, 0, reg); + gen_op_mov_v_reg(MO_32, cpu_T[0], reg); tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_v(MO_32, reg, cpu_T[0]); @@ -7298,7 +7293,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); if (mod == 3) { - gen_op_mov_TN_reg(MO_32, 0, rm); + gen_op_mov_v_reg(MO_32, cpu_T[0], rm); /* sign extend */ if (d_ot == MO_64) tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); @@ -7437,7 +7432,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); @@ -7474,7 +7469,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; if (b & 2) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, cpu_T[0], rm); gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s);