From patchwork Thu Nov 7 01:04:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 289126 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E42F12C00C1 for ; Thu, 7 Nov 2013 13:40:55 +1100 (EST) Received: from localhost ([::1]:37034 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeEK2-0004H3-7A for incoming@patchwork.ozlabs.org; Wed, 06 Nov 2013 20:23:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE4J-0008Ed-0G for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE4D-0006Mv-66 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:30 -0500 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]:42258) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE4C-0006Mq-QH for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:25 -0500 Received: by mail-pb0-f44.google.com with SMTP id rp8so311361pbb.3 for ; Wed, 06 Nov 2013 17:07:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=aWn+YbHVeNLWAs8Ta0Ga8BV2SEUyMvYYzDMtUYamqec=; b=V4r3pDYt45SaGiYv1P1cRly/rbup1NIqGYRQ56R8in0jLjYREBIGfCrbIhaWNWWN9x 9Dpro9kvrGpqmBjgXDvao2YcMpwSiJp9P6YxhP+HhQDSrAego0KIgiXumO0Lk5DF5k/Q fCT6+nKVF7E8psR3DIrRM5DkFSRQ9qwUrBrm6JFS4o1IRlz/4mdTweVeoWwDfZ+AsqN9 RM0NJCbupAG6GBBvqez0cJgBGoQHHxk7Pr+6q0UUtG1gcZIYic5d4roK3NWWY4VP3Uoo XnyJtC00BzmGisxfTK9WMum2voTsHZbmLu7TGSl9cNh6XrKsSYrvy0G8RqOOhfOPN/0c eRuQ== X-Received: by 10.66.25.6 with SMTP id y6mr224367paf.180.1383786443740; Wed, 06 Nov 2013 17:07:23 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.07.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:04:54 +1000 Message-Id: <1383786324-18415-32-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::22c Subject: [Qemu-devel] [PATCH for-1.8 31/61] target-i386: Remove gen_op_andl_A0_ffff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Replace it with tcg_gen_ext16u_tl, and in two cases merge with a previous move from cpu_regs. Signed-off-by: Richard Henderson --- target-i386/translate.c | 33 +++++++++++++-------------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index e71b1c0..5a8637b 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_andl_A0_ffff(void) -{ - tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); -} - #ifdef TARGET_X86_64 #define NB_OP_SIZES 4 @@ -568,8 +563,7 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s) /* 16 address, always override */ if (override < 0) override = R_DS; - gen_op_movl_A0_reg(R_ESI); - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]); gen_op_addl_A0_seg(s, override); } } @@ -589,8 +583,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s) gen_op_movl_A0_reg(R_EDI); } } else { - gen_op_movl_A0_reg(R_EDI); - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]); gen_op_addl_A0_seg(s, R_ES); } } @@ -2050,7 +2043,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) } if (disp != 0) gen_op_addl_A0_im(disp); - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); no_rm: if (must_add_seg) { if (override < 0) { @@ -2385,7 +2378,7 @@ static void gen_push_T0(DisasContext *s) gen_op_addl_A0_seg(s, R_SS); } } else { - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); gen_op_addl_A0_seg(s, R_SS); } @@ -2425,7 +2418,7 @@ static void gen_push_T1(DisasContext *s) gen_op_addl_A0_seg(s, R_SS); } } else { - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); gen_op_addl_A0_seg(s, R_SS); } gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); @@ -2452,7 +2445,7 @@ static void gen_pop_T0(DisasContext *s) if (s->addseg) gen_op_addl_A0_seg(s, R_SS); } else { - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); gen_op_addl_A0_seg(s, R_SS); } gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0); @@ -2475,7 +2468,7 @@ static void gen_stack_A0(DisasContext *s) { gen_op_movl_A0_reg(R_ESP); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); if (s->addseg) gen_op_addl_A0_seg(s, R_SS); @@ -2488,7 +2481,7 @@ static void gen_pusha(DisasContext *s) gen_op_movl_A0_reg(R_ESP); gen_op_addl_A0_im(-16 << s->dflag); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); if (s->addseg) gen_op_addl_A0_seg(s, R_SS); @@ -2506,7 +2499,7 @@ static void gen_popa(DisasContext *s) int i; gen_op_movl_A0_reg(R_ESP); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); if (s->addseg) @@ -2557,7 +2550,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_movl_A0_reg(R_ESP); gen_op_addl_A0_im(-opsize); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); if (s->addseg) gen_op_addl_A0_seg(s, R_SS); @@ -4417,7 +4410,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, { gen_op_movl_A0_reg(R_EDI); if (s->aflag == 0) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); } gen_add_A0_ds_seg(s); @@ -5612,7 +5605,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); if (s->aflag == 0) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); else tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); } @@ -7365,7 +7358,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, { gen_op_movl_A0_reg(R_EAX); if (s->aflag == 0) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); } gen_add_A0_ds_seg(s); gen_helper_monitor(cpu_env, cpu_A0);