From patchwork Thu Nov 7 01:04:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 289080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1566B2C0077 for ; Thu, 7 Nov 2013 12:14:05 +1100 (EST) Received: from localhost ([::1]:36849 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE6X-00014L-3h for incoming@patchwork.ozlabs.org; Wed, 06 Nov 2013 20:09:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37417) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE39-0006mI-KD for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE32-0005us-Av for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:19 -0500 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:44327) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE31-0005t1-V2 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:12 -0500 Received: by mail-pa0-f43.google.com with SMTP id hz1so476016pad.2 for ; Wed, 06 Nov 2013 17:06:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=8pT2SQGj9GNp3ZyJi5fFwK+UIl2sO2Yv7JsZc5dkMcQ=; b=b01u+Cs/P5jnzHKD4QZKT6Cm/rdcdBYKTyuW18PLPxFHphxUFHRYeB9CJjHQqZbs9g geEcMsN+wdubvLu31nIWe4Bd4d998Gpb2cSrwTVrVDRO8ek8V9cAuUbukTh5vgElkrRB q8X7PrCq42EgLlItFwhEWcS8W6T7duSWFrAlFQURKGVLcPO/5DLu1bxCHCt68AO2xMK7 hHVriDS0HcKhrrXF5tVibMk2/5FOaquy6fEcQeaHdIttiXciIT83Ky3pQPi1ACcYWoQ+ btRf2YGXcx8j6VggAG7AfCC7/G232ZXC2xwsbEWJkCbWrciWTdL18BLC3+c6sP0X23rO ebdw== X-Received: by 10.68.40.169 with SMTP id y9mr200818pbk.193.1383786371086; Wed, 06 Nov 2013 17:06:11 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.06.08 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:06:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:04:26 +1000 Message-Id: <1383786324-18415-4-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22b Subject: [Qemu-devel] [PATCH for-1.8 03/61] target-i386: Stop encoding DisasContext.mem_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Now that we don't combine mem_index with operand size info, we don't need to encode it. Which tidies many places that access it. Signed-off-by: Richard Henderson --- target-i386/translate.c | 67 ++++++++++++++++++------------------------------- 1 file changed, 25 insertions(+), 42 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 2d6b9e4..57a1659 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -586,7 +586,7 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg) static inline void gen_op_lds_T0_A0(DisasContext *s, int idx) { - int mem_index = (s->mem_index >> 2) - 1; + int mem_index = s->mem_index; switch(idx & 3) { case OT_BYTE: tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); @@ -603,7 +603,7 @@ static inline void gen_op_lds_T0_A0(DisasContext *s, int idx) static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) { - int mem_index = (s->mem_index >> 2) - 1; + int mem_index = s->mem_index; switch(idx & 3) { case OT_BYTE: tcg_gen_qemu_ld8u(t0, a0, mem_index); @@ -642,7 +642,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx) static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) { - int mem_index = (s->mem_index >> 2) - 1; + int mem_index = s->mem_index; switch(idx & 3) { case OT_BYTE: tcg_gen_qemu_st8(t0, a0, mem_index); @@ -2846,21 +2846,19 @@ static void gen_jmp(DisasContext *s, target_ulong eip) static inline void gen_ldq_env_A0(DisasContext *s, int offset) { - int mem_index = (s->mem_index >> 2) - 1; - tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); + tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); } static inline void gen_stq_env_A0(DisasContext *s, int offset) { - int mem_index = (s->mem_index >> 2) - 1; tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); - tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); + tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index); } static inline void gen_ldo_env_A0(DisasContext *s, int offset) { - int mem_index = (s->mem_index >> 2) - 1; + int mem_index = s->mem_index; tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); @@ -2870,7 +2868,7 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset) static inline void gen_sto_env_A0(DisasContext *s, int offset) { - int mem_index = (s->mem_index >> 2) - 1; + int mem_index = s->mem_index; tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); @@ -3905,15 +3903,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, break; case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ - tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + offsetof(XMMReg, XMM_L(0))); break; case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ - tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index); tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + offsetof(XMMReg, XMM_W(0))); break; @@ -4373,8 +4369,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) gen_op_mov_reg_T0(ot, rm); else - tcg_gen_qemu_st8(cpu_T[0], cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index); break; case 0x15: /* pextrw */ tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, @@ -4382,8 +4377,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) gen_op_mov_reg_T0(ot, rm); else - tcg_gen_qemu_st16(cpu_T[0], cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index); break; case 0x16: if (ot == OT_LONG) { /* pextrd */ @@ -4394,8 +4388,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) gen_op_mov_reg_v(ot, rm, cpu_T[0]); else - tcg_gen_qemu_st32(cpu_T[0], cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index); } else { /* pextrq */ #ifdef TARGET_X86_64 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, @@ -4405,7 +4398,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); else tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + s->mem_index); #else goto illegal_op; #endif @@ -4417,15 +4410,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) gen_op_mov_reg_T0(ot, rm); else - tcg_gen_qemu_st32(cpu_T[0], cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index); break; case 0x20: /* pinsrb */ if (mod == 3) gen_op_mov_TN_reg(OT_LONG, 0, rm); else - tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index); tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, xmm_regs[reg].XMM_B(val & 15))); break; @@ -4435,8 +4426,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State,xmm_regs[rm] .XMM_L((val >> 6) & 3))); } else { - tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); } tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, @@ -4464,8 +4454,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) gen_op_mov_v_reg(ot, cpu_tmp0, rm); else - tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, @@ -4476,7 +4465,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); else tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + s->mem_index); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offsetof(CPUX86State, xmm_regs[reg].XMM_Q(val & 1))); @@ -6070,8 +6059,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); break; case 2: - tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index); gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); break; case 3: @@ -6109,8 +6097,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); break; case 2: - tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index); gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); break; case 3: @@ -6131,8 +6118,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 2: gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); - tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index); break; case 3: default: @@ -6157,8 +6143,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 2: gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); - tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index); break; case 3: default: @@ -6230,14 +6215,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fpop(cpu_env); break; case 0x3d: /* fildll */ - tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index); gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); break; case 0x3f: /* fistpll */ gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); - tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, - (s->mem_index >> 2) - 1); + tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index); gen_helper_fpop(cpu_env); break; default: @@ -8315,7 +8298,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, /* select memory access functions */ dc->mem_index = 0; if (flags & HF_SOFTMMU_MASK) { - dc->mem_index = (cpu_mmu_index(env) + 1) << 2; + dc->mem_index = cpu_mmu_index(env); } dc->cpuid_features = env->features[FEAT_1_EDX]; dc->cpuid_ext_features = env->features[FEAT_1_ECX];