Patchwork [for-1.8,03/61] target-i386: Stop encoding DisasContext.mem_index

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Submitter Richard Henderson
Date Nov. 7, 2013, 1:04 a.m.
Message ID <1383786324-18415-4-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/289080/
State New
Headers show

Comments

Richard Henderson - Nov. 7, 2013, 1:04 a.m.
Now that we don't combine mem_index with operand size info,
we don't need to encode it.  Which tidies many places that
access it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-i386/translate.c | 67 ++++++++++++++++++-------------------------------
 1 file changed, 25 insertions(+), 42 deletions(-)

Patch

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 2d6b9e4..57a1659 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,7 +586,7 @@  static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
 
 static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
+    int mem_index = s->mem_index;
     switch(idx & 3) {
     case OT_BYTE:
         tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
@@ -603,7 +603,7 @@  static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
 
 static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
+    int mem_index = s->mem_index;
     switch(idx & 3) {
     case OT_BYTE:
         tcg_gen_qemu_ld8u(t0, a0, mem_index);
@@ -642,7 +642,7 @@  static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
 
 static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
+    int mem_index = s->mem_index;
     switch(idx & 3) {
     case OT_BYTE:
         tcg_gen_qemu_st8(t0, a0, mem_index);
@@ -2846,21 +2846,19 @@  static void gen_jmp(DisasContext *s, target_ulong eip)
 
 static inline void gen_ldq_env_A0(DisasContext *s, int offset)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
-    tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
+    tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
 }
 
 static inline void gen_stq_env_A0(DisasContext *s, int offset)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
-    tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
+    tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
 }
 
 static inline void gen_ldo_env_A0(DisasContext *s, int offset)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
+    int mem_index = s->mem_index;
     tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
     tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -2870,7 +2868,7 @@  static inline void gen_ldo_env_A0(DisasContext *s, int offset)
 
 static inline void gen_sto_env_A0(DisasContext *s, int offset)
 {
-    int mem_index = (s->mem_index >> 2) - 1;
+    int mem_index = s->mem_index;
     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
     tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
     tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -3905,15 +3903,13 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         break;
                     case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
                     case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
-                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
-                                          (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
                         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
                         tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
                                         offsetof(XMMReg, XMM_L(0)));
                         break;
                     case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
-                        tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
-                                          (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
                         tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
                                         offsetof(XMMReg, XMM_W(0)));
                         break;
@@ -4373,8 +4369,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3)
                         gen_op_mov_reg_T0(ot, rm);
                     else
-                        tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
-                                        (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
                     break;
                 case 0x15: /* pextrw */
                     tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
@@ -4382,8 +4377,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3)
                         gen_op_mov_reg_T0(ot, rm);
                     else
-                        tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
-                                        (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
                     break;
                 case 0x16:
                     if (ot == OT_LONG) { /* pextrd */
@@ -4394,8 +4388,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         if (mod == 3)
                             gen_op_mov_reg_v(ot, rm, cpu_T[0]);
                         else
-                            tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
-                                            (s->mem_index >> 2) - 1);
+                            tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
                     } else { /* pextrq */
 #ifdef TARGET_X86_64
                         tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
@@ -4405,7 +4398,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                             gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
                         else
                             tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
-                                            (s->mem_index >> 2) - 1);
+                                              s->mem_index);
 #else
                         goto illegal_op;
 #endif
@@ -4417,15 +4410,13 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3)
                         gen_op_mov_reg_T0(ot, rm);
                     else
-                        tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
-                                        (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
                     break;
                 case 0x20: /* pinsrb */
                     if (mod == 3)
                         gen_op_mov_TN_reg(OT_LONG, 0, rm);
                     else
-                        tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
-                                        (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
                     tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
                                             xmm_regs[reg].XMM_B(val & 15)));
                     break;
@@ -4435,8 +4426,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                                         offsetof(CPUX86State,xmm_regs[rm]
                                                 .XMM_L((val >> 6) & 3)));
                     } else {
-                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
-                                        (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
                         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
                     }
                     tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
@@ -4464,8 +4454,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         if (mod == 3)
                             gen_op_mov_v_reg(ot, cpu_tmp0, rm);
                         else
-                            tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
-                                            (s->mem_index >> 2) - 1);
+                            tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
                         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
                         tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
                                         offsetof(CPUX86State,
@@ -4476,7 +4465,7 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                             gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
                         else
                             tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
-                                            (s->mem_index >> 2) - 1);
+                                              s->mem_index);
                         tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
                                         offsetof(CPUX86State,
                                                 xmm_regs[reg].XMM_Q(val & 1)));
@@ -6070,8 +6059,7 @@  static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
                         gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
                         break;
                     case 2:
-                        tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 
-                                          (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
                         gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
                         break;
                     case 3:
@@ -6109,8 +6097,7 @@  static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
                         gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
                         break;
                     case 2:
-                        tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 
-                                          (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
                         gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
                         break;
                     case 3:
@@ -6131,8 +6118,7 @@  static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
                         break;
                     case 2:
                         gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
-                        tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 
-                                          (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
                         break;
                     case 3:
                     default:
@@ -6157,8 +6143,7 @@  static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
                         break;
                     case 2:
                         gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
-                        tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 
-                                          (s->mem_index >> 2) - 1);
+                        tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
                         break;
                     case 3:
                     default:
@@ -6230,14 +6215,12 @@  static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
                 gen_helper_fpop(cpu_env);
                 break;
             case 0x3d: /* fildll */
-                tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 
-                                  (s->mem_index >> 2) - 1);
+                tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
                 gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
                 break;
             case 0x3f: /* fistpll */
                 gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
-                tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 
-                                  (s->mem_index >> 2) - 1);
+                tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
                 gen_helper_fpop(cpu_env);
                 break;
             default:
@@ -8315,7 +8298,7 @@  static inline void gen_intermediate_code_internal(X86CPU *cpu,
     /* select memory access functions */
     dc->mem_index = 0;
     if (flags & HF_SOFTMMU_MASK) {
-        dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
+        dc->mem_index = cpu_mmu_index(env);
     }
     dc->cpuid_features = env->features[FEAT_1_EDX];
     dc->cpuid_ext_features = env->features[FEAT_1_ECX];