From patchwork Wed Nov 6 20:31:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 289009 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A9F882C00C4 for ; Thu, 7 Nov 2013 07:37:32 +1100 (EST) Received: from localhost ([::1]:35928 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ve9r0-00059E-RY for incoming@patchwork.ozlabs.org; Wed, 06 Nov 2013 15:37:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ve9mW-00007k-7Q for qemu-devel@nongnu.org; Wed, 06 Nov 2013 15:33:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ve9mJ-0003UL-Bv for qemu-devel@nongnu.org; Wed, 06 Nov 2013 15:32:51 -0500 Received: from mail-vb0-x232.google.com ([2607:f8b0:400c:c02::232]:34158) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ve9mJ-0003UD-7H; Wed, 06 Nov 2013 15:32:39 -0500 Received: by mail-vb0-f50.google.com with SMTP id x16so17692vbf.37 for ; Wed, 06 Nov 2013 12:32:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NyGUG8WOwinS3B7lq1n/TDiw5D0vTPZyN6WM7dTDhtI=; b=Zl/Qz5P72BOMIHL9zQ6eOPxFNb1bdtVMepSSpz+/wUPyq14gLd/I8GFHbjNsVFMlki 5vsB9B6I8/W0wHI4E4LO1gxS0ta4984EMAHlmCl1/nNxdfK/0w5UTB9VdMoSmDg6dw9a J3UTVoMwdK6Of7sYtALohfYEgcH0A+vkvW2jvEbgeA+3nECkY2gUBHL2GFSXKHzadU13 g/ZLKoDj8YRcYXF5GNI1p7dOH2XFR9YI7+ofgtdHWaWExrMBNHcy8W9VFetIqWn6iZtt VpQf8Thzch7Fm88xgJqKFPC6mK7Bsy7R9UkrIGIJuQRUG2Uc1qnkqFImsMkUTPha5uEh 6Gcg== X-Received: by 10.58.181.230 with SMTP id dz6mr175026vec.35.1383769958802; Wed, 06 Nov 2013 12:32:38 -0800 (PST) Received: from tmusta-sc.rchland.ibm.com (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id rx6sm28375094vec.6.2013.11.06.12.32.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 Nov 2013 12:32:38 -0800 (PST) From: Tom Musta To: qemu-devel@nongnu.org, tommusta@gmail.com Date: Wed, 6 Nov 2013 14:31:48 -0600 Message-Id: <1383769916-5582-7-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383769916-5582-1-git-send-email-tommusta@gmail.com> References: <1383769916-5582-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400c:c02::232 Cc: qemu-ppc@nongnu.org Subject: [Qemu-devel] [PATCH 06/14] VSX Stage 4: Add xsaddsp and xssubsp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and VSX Scalar Subtract Single-Precision (xssubsp) instructions. The existing VSX_ADD_SUB macro is modified to support the rounding of the (intermediate) result to single-precision. Signed-off-by: Tom Musta --- target-ppc/fpu_helper.c | 21 ++++++++++++++------- target-ppc/helper.h | 3 +++ target-ppc/translate.c | 6 ++++++ 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index f3d02cc..7b4958a 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1768,7 +1768,7 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \ +#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \ void helper_##name(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xa, xb; \ @@ -1794,6 +1794,11 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ } \ } \ \ + if (r2sp) { \ + float32 tmp32 = float64_to_float32(xt.fld[i], &env->fp_status); \ + xt.fld[i] = float32_to_float64(tmp32, &env->fp_status); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[i], sfprf); \ } \ @@ -1802,12 +1807,14 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1) -VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0) -VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0) -VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1) -VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0) -VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0) +VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0) +VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1) +VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0) +VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0) +VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0) +VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1) +VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0) +VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0) /* VSX_MUL - VSX floating point multiply * op - instruction mnemonic diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 0276b02..696b9d3 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -286,6 +286,9 @@ DEF_HELPER_2(xsrdpim, void, env, i32) DEF_HELPER_2(xsrdpip, void, env, i32) DEF_HELPER_2(xsrdpiz, void, env, i32) +DEF_HELPER_2(xsaddsp, void, env, i32) +DEF_HELPER_2(xssubsp, void, env, i32) + DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) DEF_HELPER_2(xvmuldp, void, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 62604fd..bd639cc 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7341,6 +7341,9 @@ GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) + GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) @@ -10148,6 +10151,9 @@ GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), +GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), +GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), + GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),