From patchwork Tue Nov 5 17:22:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 288594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42BF12C033B for ; Wed, 6 Nov 2013 04:22:53 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754898Ab3KERWp (ORCPT ); Tue, 5 Nov 2013 12:22:45 -0500 Received: from e06smtp10.uk.ibm.com ([195.75.94.106]:50829 "EHLO e06smtp10.uk.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754624Ab3KERWn (ORCPT ); Tue, 5 Nov 2013 12:22:43 -0500 Received: from /spool/local by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 5 Nov 2013 17:22:40 -0000 Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by d06dlp02.portsmouth.uk.ibm.com (Postfix) with ESMTP id EEBF9219005E; Tue, 5 Nov 2013 17:22:38 +0000 (GMT) Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by b06cxnps4076.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id rA5HMQY862521526; Tue, 5 Nov 2013 17:22:26 GMT Received: from d06av07.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id rA5HMcGN032303; Tue, 5 Nov 2013 12:22:38 -0500 Received: from smtp.lab.toulouse-stg.fr.ibm.com (srv01.lab.toulouse-stg.fr.ibm.com [9.101.4.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id rA5HMbGp032300; Tue, 5 Nov 2013 12:22:38 -0500 Received: from hermes.lab.toulouse-stg.fr.ibm.com (hermes.lab.toulouse-stg.fr.ibm.com [9.101.4.42]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id C0E71210FFE; Tue, 5 Nov 2013 18:22:37 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: agraf@suse.de, paulus@samba.org Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Benjamin Herrenschmidt Subject: [PATCH v5 5/6] powerpc: add Split Little Endian bit to MSR Date: Tue, 5 Nov 2013 18:22:07 +0100 Message-Id: <1383672128-26795-6-git-send-email-clg@fr.ibm.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1383672128-26795-1-git-send-email-clg@fr.ibm.com> References: <1383672128-26795-1-git-send-email-clg@fr.ibm.com> In-Reply-To: <84018BDE-858B-4F59-8AA0-9135CCFF4720@suse.de> References: <84018BDE-858B-4F59-8AA0-9135CCFF4720@suse.de> MIME-Version: 1.0 X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13110517-4966-0000-0000-00000767EB28 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Architecture 2.07 defines a new MSR Split Little Endian (SLE) bit, which changes the order used for data storage accesses. If MSR[SLE] is 0, instruction and data storage accesses for the thread are the same and use the value specified by MSR[LE]. If MSR[SLE] is 1, instruction and data storage accesses for the thread are opposite. Instruction storage accesses use the value specified by MSR[LE]. Data storage accesses use the value specified by ~MSR[LE]. The table below illustrates the Endian modes for all combinations of MSR[SLE] and MSR[LE]. SLE LE Data Instruction 0 0 Big Big 0 1 Little Little 1 0 Little Big 1 1 Big Little Signed-off-by: Cédric Le Goater Cc: Benjamin Herrenschmidt --- This is clearly a powerpc patch but the following patch is for kvm-ppc and it depends on it. I am not sure how to handle the patch serie. Should I send to linuxppc-dev@lists.ozlabs.org also ? Thanks, C. arch/powerpc/include/asm/reg.h | 3 +++ arch/powerpc/kernel/process.c | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 5c45787..1464ef9 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -29,6 +29,7 @@ #define MSR_SF_LG 63 /* Enable 64 bit mode */ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ +#define MSR_SLE_LG 58 /* Split Little Endian */ #define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */ #define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ #define MSR_TS_LG 33 /* Trans Mem state (2 bits) */ @@ -68,11 +69,13 @@ #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ +#define MSR_SLE __MASK(MSR_SLE_LG) /* Split Little Endian */ #else /* so tests for these bits fail on 32-bit */ #define MSR_SF 0 #define MSR_ISF 0 #define MSR_HV 0 +#define MSR_SLE 0 #endif #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 5c466aa..7f87981 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -799,6 +799,7 @@ static struct regbit { #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) {MSR_SF, "SF"}, {MSR_HV, "HV"}, + {MSR_SLE, "SLE"}, #endif {MSR_VEC, "VEC"}, {MSR_VSX, "VSX"},